Intel Corporation

Zvika Greenfield

Christopher P Mozak

Theodore Zale Schoenborn

Israel Diamand

Kuljit Singh Bains

John B Halbert

Anant V Nori

Aravindh V Anantaraman

Julius Yuli Mandelblat

Nadav Bonen

Asaf Rubinstein

Tomer Levy

Randy B Osborne

Robert J Royer, Jr

Shlomo Raikin

Jayesh Gaur

David G Ellis

Daniel Greenspan

Eran Shifer

Supratik Majumder

Nir Misgav

Joydeep Ray

David M Durham

Shay Gueron

Uday R Savagaonkar

Carlos V Rozas

Francis X Mckeen

Blaise B Fanning

Sreenivas Subramoney

Ittai Anati

Alaa R Alameldeen

Lily Pao Looi

Zeshan A Chishti

Bruce Querbach

Jacob Doweck

Chia-Hung Sophia Kuo

Moshe Maor

Todd M Witter

Suneeta Sah

Dale J Juenemann

Bryan L Spry

Ariel Berkovits

Sowmiya Jayachandran

James A Boyd

Jay Joseph Nejedlo

Alexey Kostinsky

Ofir Mulla

Philip Abraham

James M Shehadi

Christopher E Yunker

Sahar Khalili

Pavel Konev

Dimpesh Patel

Jayasekhar Tholiyil

Evgeny Bolotin

Rony Ghattas

Eshel Serlin

Eli Abadi

Srinivas Santosh Kumar Madugula

Pradeep Ramachandran

Dannie G Feekes

Olga Fomenko

Charles D Lucas

Gary C Chow

A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

Multi-level system memory with near memory capable of storing compressed cache lines

A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.

Dynamically changing between latency-focused read operation and bandwidth-focused read operation

A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.

Fast page fault handling process implemented on persistent memory

An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures

Embodiments of the present disclosure are directed towards a computing device having a cache memory device with a scrubber logic. In some embodiments, the scrubber logic controller may be coupled with the cache device, and may perform a selection for eviction from the cache device a portion of data stored in the cache device, based at least in part on one or more selection criteria, at a dynamically adjusted level of aggressiveness of the selection performance. The scrubber logic controller may adjust the level of aggressiveness of the selection performance, based at least in part on a determined time left to complete the selection performance at a current level of aggressiveness. Other embodiments may be described and/or claimed.

Cache memory with scrubber logic

Interleaved cache controllers with shared metadata are disclosed and described. A memory system may comprise a plurality of cache controllers and a metadata store interconnected by a metadata store fabric. The metadata store receives information from at least one of the plurality of cache controllers, a portion of which is stored as shared distributed metadata. The metadata store provides shared access of the shared distributed metadata hosted to the plurality of cache controllers.

Interleaved cache controllers with shared metadata and related devices and systems

Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

Concurrent accesses of asymmetrical memory sources

An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.

Operating system transparent system memory abandonment

Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction watermark, an eviction process is triggered for evicting a superline from a sectored cache storing at least one superline. An eviction candidate is selected from superlines that have: 1) a sector usage below or equal to a superline low watermark and 2) an RT timestamp that is greater than a superline age watermark.

Sparse superline removal

A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as 'hammered' or a 'row hammer event'), physically adjacent row (a &#x201c;victim&#x201d; row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Row hammer refresh command

An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.

Memory controller for multi-level system memory with coherency unit

An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.

Using data pattern to mark cache lines as invalid

Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in the cache memory, perform a lookup operation for the first data element in the volatile memory and in response to a failed lookup operation, to generate a cache scrub hint forward the cache scrub hint to a cache scrub engine and identify one or more cache lines to scrub based at least in part on the cache scrub hint. Other examples are also disclosed and claimed.

Managing sectored cache

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Kfar Sava, Israel

Zvika Greenfield