Quick Technologies Ltd.

Chip Express (israel) Ltd.

Elron Electronic Industries Ltd.

Other

Elbit Computers Ltd.

Zvi Orbach

Meir I Janai

Uzi Yoeli

Eran Rotem

Gideon Amir

Zeev Ganor

Miguel O Simerman

Alon Kapel

Shlomo Idan

Sharon Zehavi

Lea Ziph

Ofer Hareuveni

This invention discloses an integrated circuit device including transistors having predetermined upper voltage limits, a multi-layer metal interconnect structure connecting the transistors to each other and to an external voltage source having a voltage in excess of the predetermined upper voltage limits of a first plurality of the transistors, and a voltage reducer connected along the interconnect structure between the external voltage source and the first plurality of the transistors.

Low voltage device operable with a high voltage supply

A customizable logic array device including an array of identical multiple input, function selectable logic cells comprising a first conductive layer, application configurable interconnection apparatus selectably interconnecting the multiple input, function selectable logic cells, the application configurable interconnection apparatus comprising at least two conductive layers.

Customizable logic array device

This invention discloses a gate array device, useful either as a configurable gate array device or a compact gate array device, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, said grid comprising a bottom metal layer and at least one metal layer disposed over the bottom metal layer, power and ground lines formed of said bottom metal layer, extending generally parallel to said columns and a routing grid interconnecting said clusters of macrocells, said routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal tracks are employed to connect to each logic cell.

Mapping of gate arrays

A very high speed customizable logic array device comprising:

High speed customizable logic array device

Three metal layer customizable gate array devices and techniques to customize them are disclosed. Such a device incorporates an integrated circuit blank having a plurality of transistors and at least three metal layers. A plurality of fusible links interconnects said plurality of transistors into an inoperable circuit. A laser ablative etch resistant coating is formed over the device. Later, the coating is ablated by laser at locations overlaying designated fuse locations. The device is then etched for selectably removing some of the fusible links, thereby converting the inoperable integrated circuit blank into an operable gate array device.

Customizable three metal layer gate array devices

Customizable semiconductor devices, integrated circuit gate arrays and techniques to produce same are disclosed. The devices comprise integrated circuit blanks having a collection of semiconductor elements and at least one metal layer including fusible links interconnecting said collection of semiconductor elements into an inoperably connected integrated circuit blank. At least one metal layer is first etched thereby to define a pattern of conductors. A passivation layer is provided over at least one metal layer, afterwhich at least one metal layer is etched a second time for selectably removing the fusible links, thereby converting the inoperable integrated circuit blank into a selected operable electronic function.

Personalizable gate array devices

Customizable semiconductor/devices, integrated circuit gate arrays and techniques to produce same are disclosed. The devices comprise integrated circuit blanks having a collection of semiconductor elements and at least one metal layer including fusible links interconnecting said collection of semiconductor elements into an inoperably connected integrated circuit blank. At least one metal layer is first etched thereby to define a pattern of conductors. A passivation layer is provided over at least one metal layer, afterwhich at least one metal layer is etched a second time for selectably removing the fusible links, thereby converting the inoperable integrated circuit blank into a selected operable electronic function.

A personalizable multi-chip carrier including a substrate, first and second pluralities of conductors arranged on respective first and second parallel planes, the first and second pluralities of conductors defining a grid of conductors arranged over the substrate and defining a multiplicity of crossing locations at which conductors of the first and second pluralities cross each other, apparatus for interconnecting the first and second pluralities of conductors at locations adjacent the multiplicity of crossing locations and including a plurality of fusible links.

Personalizable multi-chip carrier including removable fuses

A programmable integrated circuit for prototyping applications including a first patterned metal layer, an insulation layer formed over the first metal layer and a second patterned metal layer formed over the insulation layer, the first and second patterned metal layers being formed with selectably removable regions, the insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions a coating comprising a layer of a dielectric material of high laser radiation absorption coefficient.

Ablative etch resistant coating for laser personalization of integrated

A selectably customizable semiconductor device including a first metal layer disposed in a first plane and including first elongate strips extending parallel to a first axis, a second metal layer disposed in a second plane generally parallel to and electrically insulated from said first plane and including second elongate strips extending parallel to a second axis, the second axis being generally perpendicular to the first axis, whereby a multiplicity of elongate strip overlap locations are defined at which the elongate strips of the first and second metal layers overlap in electrical insulating relationship;

Routing structure for a customizable integrated circuit

Stabilized pulsed laser apparatus including pulsed laser means providing an output beam including a plurality of pulses, a pulse controller providing control instructions to the laser, and an attenuator for selectably performing attenuation of the output beam of the pulsed laser means in response to at least the time interval between a given pulse and the pulse preceding it, for maintaining at least one desired energy characteristic notwithstanding changes in at least the time interval.

Pulsed laser system

An integrated circuit which is readily customized by the user to his specific requirements and is thus suitable for prototype and small scale production.

Fabrication of personalizable integrated circuits

A selectably customizable semconductor device including a first metal layer disposed in a first plane and including first elongate strips extending parallel to a first axis, a second metal layer disposed in a second plane generally parallel to and electrically insulated from the first plane and including second elongate strips extending parallel to a second axis, the second axis being generally perpendicular to the first axis, whereby a multiplicity of elongate strip overlap locations are defined at which the elongate strips of the first and second metal layers overlap in electrical insulating relationship, the first metal layer including a plurality of fusible conductive bridges joining adjacent pairs of the first elongate strips, the fusible conductive bridges including first and second fusible links, the first metal layer also including a plurality of branch strips, each branch strip connecting one of the fusible conductive bridges at a location intermediate the first and second fusible links to a branch overlap location spaced from the multiplicity of elongate strip overlap locations, an electrical connection being formed between the first metal layer and the second metal layer at each of the branch overlap locations.

Customizable semiconductor devices

A method of moving along a travel axis and in a selected direction a driven member comprising the steps of providing translation apparatus including a driver mounted in a fixed position relative to a base, the driver comprising selectably operable forward, center and rear elements coupled in series and associated with the driven member and being arranged parallel to the travel axis, the forward and rear elements comprising apparatus for clamping the driven member and the center element comprising apparatus for varying the distance between the forward and rear elements; and in a series of distinct steps, operating the forward, center and rear elements so as to cause movement of the driven member relative to the base including, steps of operation, partially overlapping in time, of the forward and center elements and the center and rear elements and steps of operation, non-overlapping in time, of the forward and rear elements.

Growing community of inventors

Haifa, Israel

Zvi Orbach