Monolithic 3d Inc.

Zeno Semiconductor, Inc.

Other

Easic Corporation

Or-ment LLC

William Marsh Rice University

Casic Corporation

Grigore, George Catalin

Kapel, Alon

Zvi Or-Bach

Brian Cronquist

Deepak Chandra Sekar

Jin-Woo Han

Yuniarto Widjaja

Zeev Wurman

Tal Isaac Lavian

Israel Beinglass

Jan Lodewijk De Jong

Eli Lusky

Ze'ev Wurman

Paul G Lim

Benjamin S Louie

Adrian Apostol

Richard Zeman

Adam E Levinthal

Romeo Iacobut

Laurence Hager Cooke

Dinesh Maheshwari

Ilan Yehuda Granot

Isreal Beinglass

Petrica Avram

Laurance Cooke

Dan Kikinis

James Mitchell Tour

Jun Yao

Bill Douglas Cox

J L De Jong

Adam H Leventhal

Albert Karl Henning

George Grigore

Stan Mihelcic

Alexander Sinitskiy

Alon Kapel

Joseph Salzman

Elvira Beitler

Ze′ev Wurman

George Catalin Grigore

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.

3D semiconductor device and structure with three levels and isolation layers

A semiconductor device including: a first level including memory control circuits (include a plurality of refresh circuits for the memory units) which include first transistors; a second level including a first array of memory cells including second transistors self-aligned to at least one of the third transistors; a third level disposed on top of the second level disposed on top of first level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, second level is bonded to the first level, a plurality of slits disposed through the second level, the third level, and the fourth level, the slits enable gate replacement of a plurality of the third transistors, where the second array of memory cells include a plurality of independently controlled memory units.

3D semiconductor devices and structures with slits

A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed above the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one power down control circuit, and where the device includes a hybrid bonding layer.

3D semiconductor memory devices and structures

A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors and is disposed on top of the first level; levels connection pads (LCPs) disposed between the first level and second level; providing placement of the LCPs; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement of the LCPs, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool.

Automation methods for 3D integrated circuits and devices

An electromagnetic wave medical imaging system, the system including: at least one antenna; transmission electronics; receiving electronics; receiving computing electronics, where the transmission electronics are structured to transmit a first electromagnetic wave having an Orbital Angular Momentum wave-front thru the antenna towards a target, where the Orbital Angular Momentum wave-front includes a vortex region, where the receiving computing electronics are structured to form a first signal from a first return wave of the first electromagnetic wave; and an image sensor integrated with the antenna, where the system is designed to operate at a near field electromagnetic wave.

Electromagnetic wave medical imaging system, device, and methods

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors each of which includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors and overlaying the second metal layer, each of first memory cells include at least one second transistor; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors and overlaying the third level, each of second memory cells include at least one fourth transistor, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one of the second transistors includes a hafnium oxide gate dielectric.

3D semiconductor device and structure with metal layers and memory cells

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the bonded includes metal to metal bonds, and where at least one of the first transistors controls power delivery to at least one of the second transistors.

3D semiconductor device and structure

A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the first level includes control of power delivery to the at least one third transistor.

Method for producing 3D semiconductor devices and structures with transistors and memory cells

A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; at least four electronic circuit units (ECUs); a redundancy circuit, where each of the at least four ECUs includes a first circuit, which includes a portion of the first transistors, where each of the at least four ECUs includes a second circuit, the second circuit including some second transistors, where each of the at least four ECUs includes a vertical connectivity structure which includes pillars, where the pillars provide electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide and metal to metal bonding regions.

3D semiconductor devices and structures with electronic circuit units

A method of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer; providing a second substrate including a second level, the second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer, the third silicon layer has an average thickness of less than 2,000 nm; forming a plurality of second transistors each including a single crystal channel; forming many metal layers interconnecting the plurality of second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second single crystal silicon layer.

Method to produce a 3D multilayer semiconductor device and structure

A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors, at least one metal layer, and third memory arrays; a fourth level disposed on top of the third level, where the fourth level includes fourth transistors, another at least one metal layer, and is bonded to the third level, where the bonded includes metal-to-metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes; and a via connection through the second level and the third level, and where the fourth level includes at least one SRAM memory array.

3D memory devices and structures with memory arrays and metal layers

A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.

3D semiconductor device and structure with metal layers

An electrical passenger car, the electrical passenger car including: a battery pack; motor control electronics; a communication control unit; at least one electrically driven motor; wheels, where the wheels are connected to the at least one electrically driven motor; and sensors, where the sensors are connected to at least the motor control electronics, where the wheels include a first wheel and a second wheel, where the second wheel has a radius at least 7% greater than a radius of the first wheel, where the battery pack is mounted in the electrical passenger car frame such that the battery pack can be moved upward or downward, and where the electrical passenger car is designed to be driven mainly on a paved road.

Efficient electrical passenger car with motor control

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.

Multilevel semiconductor device and structure with image sensors and wafer bonding

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

3D semiconductor device and structure with logic and memory

Growing community of inventors

San Jose, CA, United States of America

Zvi Or-Bach