Samsung Electronics Co., Ltd.

Zvi Guz

Ramdas P Kachare

Anahita Shayesteh

Oscar Prem Pinto

Son Truong Pham

Xuebin Yao

Fred Worley

Stephen Garry Fischer

Vikas Sinha

Vijay Balakrishnan

Liang Yin

Ming Lin

Gunneswara Rao Marripudi

A system and method for leveraging a native operating system page cache when using non-block system storage devices is disclosed. A computer may include a processor, memory, and a non-block system storage device. A file system may be stored in memory and running on the processor, which may include a page cache. A key-value file system (KVFS) may reside between the file system and the storage device and may map received file system commands to key-value system commands that may be executed by the storage device. Results of the key-value system commands may be returned to the file system, permitting the operating system to cache data in the page cache.

System and methods for providing fast cacheable access to a key-value device through a filesystem interface

According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.

Systems and methods for message tunneling

A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n&#x2212;1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.

System and method for accelerated data processing in SSDS

A system and method for leveraging a native operating system () page cache () when using non-block system storage devices () is disclosed. A computer () may include a processor (), memory (), and a non-block system storage device (). A file system () may be stored in memory () and running on the processor (), which may include a page cache (). A key-value file system (KVFS) () may reside between the file system () and the storage device () and may map received file system commands () to key-value system commands () that may be executed by the storage device (). Results of the key-value system commands () may be returned to the file system (), permitting the operating system () to cache data in the page cache ().

A method includes: receiving, at an acceleration platform manager (APM) from an application service manager (ASM), application function processing information; allocating, by the APM, a first storage processing accelerator (SPA) from a plurality of SPAs, wherein at least one SPA of the plurality of SPAs comprises a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs comprising n SPEs, enabling the plurality of SPEs in the first SPA, wherein once enabled, the at least one SPE of the plurality of SPEs in the first SPA is configured to process data based on the application function processing information; determining, by the APM, if data processing is completed by the at least one SPE of the plurality of SPEs in the first SPA; and sending, by the APM, a result of the data processing by the SPEs of the first SPA, to the ASM.

System and method for accelerated data processing in SSDs

Accelerated data processing in SSDs comprises SPAs an APM and host processor whereby the SPAs has multiple of SPEs

A host machine is disclosed. The host machine may include a host processor, a memory, an operating system running on the host processor, and an application running under the operating system on the host processor. The host machine may also include a Peripheral Component Interconnect Express (PCIe) tunnel to a Non-Volatile Memory Express (NVMe) Solid State Drive (SSD) and an RPC capture module which may capture the RPC from the application and deliver a result of the RPC to the application as though from the host processor, where the NVMe SSD may execute the RPC to generate the result.

Method for NVMe SSD based storage service using RPC and gRPC tunneling over PCIe +

A distributed storage system can include a storage node (). The storage node () can include a Solid State Drive (SSD) or other storage device that employs garbage collection (), a device garbage collection monitor (), a garbage collection coordinator (), an Input/Output (I/O) redirector (), and an I/O resynchronizer (). The device garbage collection monitor () can determine whether any storage devices () need to perform garbage collection. The garbage collection coordinator () can schedule when the storage device () can perform garbage collection. The I/O redirector () can redirect read requests () and write requests () away from the storage device () when it is performing garbage collection. The I/O resynchronizer () can ensure that data on the storage device () is up-to-date after garbage collection finishes.

Coordinated garbage collection of flash devices in a distributed storage system

A computing system includes: a write buffer block configured to: receive a data in a write buffer entry for staging the data prior to transferring the data to a storage cell, determine a validity identification of the data for a buffer entry address of the write buffer entry, store the data based on the validity identification to the write buffer entry, and a memory computing block, coupled to the write buffer block, configured to read the data for accessing the write buffer block.

Computing system with write buffer including speculative storage write and method of operation thereof

Embodiments of the inventive concept include a volatile memory device including a memory cell array, the memory cell array including multiple rows and/or banks to store data. The memory device can include an address decoder coupled to the memory cell array. The memory device can include a control logic section coupled to the address decoder. The control logic section can include a defresh logic section configured to intentionally violate, by an activate command, a row precharge time (T) and/or a row active time (T) for each of the plurality of rows to clean the data from the memory cell array. Memory data can be cleaned from the memory cell array responsive to the violations.

Growing community of inventors

Palo Alto, CA, United States of America

Zvi Guz