Analog Devices,inc.

Zvi Greenfield

Jose Fridman

Douglas Garde

Gil Zukerman

Rasekh Rifaat

Stephen J Plante

Alberto E Sandbank

Alexei Zatsman

David R Levine

Aryeh Lezerovitz

Dina Treves

Robert Koslawsky

A digital signal processor performs turbo and Virterbi channel decoding in wireless systems. The computation block of the digital signal processor is provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.

High performance turbo and Viterbi channel decoding in digital signal processors

A digital signal processor performs despread decoding in wireless telephone systems. Orthogonal codes are used to combine data signals into one overall coded signal which is transmitted. The orthogonal codes are used to retrieve individual data signals from the transmitted overall coded signal. Despread instructions are included in the digital signal processor functionality.

Despread signal recovery in digital signal processors

A method for caching specified data in an n-way set associative memory with a copy-back update policy consists of the following steps. First, a row of the associative memory, organized as a plurality of rows and having n ways per row, is selected according to the main memory address of the specified data. The main memory provides primary storage for the data being cached. If one of the ways of the selected row holds invalid data, the specified data is cached in the way holding the invalid data and the data caching process is discontinued. If all n ways of the selected row hold valid data, the following steps are performed. First, a replacement strategy is used to select a way from the selected row. If the way selected in accordance with the replacement strategy holds unmodified data, the specified data is cached in the way selected by the replacement strategy and the data caching process is discontinued. However, if the way selected by the replacement strategy holds modified data, the ways of the selected row are examined again to find a way that holds data from the currently open page of the main memory. If such at least one such way is found, the specified data is cached in one of the ways holding data from the open page, and the data caching process is discontinued. Finally, if none of the ways in the selected row meet the above criteria, the specified data is cached in the way previously selected by the replacement algorithm, and the method terminates.

Cache memory data replacement strategy

A CPU includes a number of functional units that cooperate together to execute instructions. On-chip memory is divided into several sections, each of which is connected to an associated internal bus. All of the functional units are connected to each of the internal busses so that each of the functional units can read from and write to all memory locations. To conduct a transaction with memory, a functional unit determines which memory location it requires, and then arbitrates for mastership of the bus associated with the section of memory containing that memory location. By providing two or more internal busses, two or more bus transactions can occur simultaneously. A virtual bus is provided to facilitate transactions between functional units. The virtual bus is a bus arbiter without an associated physical bus. To conduct a transaction with another functional unit, the functional unit arbitrates for mastership of the virtual bus, the virtual bus monitors the internal busses or communicates with the other bus arbiters to determine which of the internal busses is unoccupied and, upon receiving a request to access the virtual bus, assigns one of the internal busses to the requesting functional unit. Using a virtual bus is advantageous since requesting access to the virtual bus has the affect of arbitrating for each of the physical busses simultaneously. Thus, the amount of time spent arbitrating for access to the physical busses is minimized. Also, since the physical busses typically do not run at 100% capacity, allocating use of the physical busses to non-memory transactions maximizes use of the physical busses without significantly distracting from the ability of the functional units to access memory. Finally, using a virtual bus instead of an additional physical bus takes up much less space than would be required if a dedicated physical bus were provided for transactions between functional units.

Method and apparatus for communicating between multiple functional units in a computer environment

A multiprocessor system includes a distributed bus arbitration system in which bus arbitration takes place simultaneously on each of the multiple processors connected to the bus. Each processor has a local arbitrator of common configuration with the other local arbitrators and a dedicated request line. Each local arbitrator is connected to each dedicated request line to monitor signals on lines indicative of requests for mastership of the bus by the processors. Since each local arbitrator is of common configuration with the other local arbitrators, is operating synchronously with the other arbitrators, and is provided with a similar set of inputs, each arbitrator will arrive at the same conclusion as to which processor is to become bus master. Accordingly, an external bus arbitrator is not required and acknowledge lines are not required to communicate signals indicative of the result of the bus arbitration to the processors. Additionally, the number of priority request lines can be dramatically reduced by requiring a requesting processor to de-assert a bus request upon detecting a priority request by another processor. The multi processor system also includes a distributed DRAM refresh system in which each processor has a local DRAM refresh controller of common configuration with the other DRAM refresh controllers. Signals on a refresh line are monitored by each of the local DRAM refresh controllers to enable synchronous updating of local DRAM refresh counters and resets of the local DRAM refresh counters. Thus, as mastership of the bus passes from one processor to the other, the new bus master's local DRAM refresh controller can continue the DRAM refresh process without requiring information to be transferred from the old bus master to the new bus master, and without duplicating DRAM refresh operations.

DRAM refresh monitoring and cycle accurate distributed bus arbitration in a multi-processing environment

A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.

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Ksirsava, Israel

Zvi Greenfield