Boe Technology Group Co., Ltd.

Ordos Yuansheng Optoelectronics Co., Ltd.

Chengdu Boe Optoelectronics Technology Co., Ltd.

Zuqiang Wang

Chunping Long

Chien Hung Liu

Zheng Liu

Lujiang Huangfu

Liang Sun

Yuqing Yang

Hongwei Tian

Yanan Niu

Yinan Liang

Guang Cheng Li

Xueyan Tian

Yucheng Chan

Xiaoyong Lu

Jang Soon Im

Yu Cheng Chan

Won Seok Kim

Zhengping Xiong

Jangsoon Im

A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation of forming a low temperature poly silicon active layer; a substrate has a first region and a second region; and the step includes: forming a buffer layer on the first region and the second region of the substrate, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region; or, forming the buffer layer on the first region of the substrate; forming an amorphous silicon layer on the buffer layer; performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer; and removing the poly silicon layer on the second region, and forming the low temperature poly silicon active layer on the first region.

Thin film transistor and preparation method thereof, array substrate and display apparatus

A display panel includes: a base substrate; a peripheral circuit located on the base substrate, the peripheral circuit including a first circuit, a second circuit and a third circuit, and the first circuit, the second circuit and the third circuit respectively including a first electrode pattern, a second electrode pattern and a third electrode pattern; and a protection structure, located in at least one circuit of the first circuit, the second circuit and the third circuit and configured for preventing an electrode pattern from being disconnected.

Display panel

Pixel unit, array substrate, and display device, and their fabrication methods are provided. The disclosed pixel unit can include: a transistor, including a drain electrode; a pixel electrode, including a first bottom conductive layer in contact with a surface of the drain electrode and a metal layer; and a planarization layer, formed on the transistor and the first bottom conductive layer. The metal layer is electrically connected to the first bottom conductive layer through a via-hole in the planarization layer.

Pixel unit, array substrate, and display device, and fabrication methods thereof

Embodiments of the present invention provides an array substrate. The array substrate includes a display region and a packaging region. The packaging region includes a plurality of functional layers. And the packaging region further includes: a plurality of through holes running through at least one of the plurality of functional layers and configured to allow a packaging adhesive to enter therein; and a groove formed above at least some of the through holes, wherein, projection areas of the at least some of the through holes onto a base substrate of the array substrate are located within a projection area of the groove onto the base substrate. Embodiments of the present invention further provides a display panel and a display apparatus including the abovementioned array substrate, and a method of manufacturing the abovementioned array substrate.

Array substrate and methods of manufacturing same, and display panel and display apparatus including the array substrate

A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.

Polysilicon thin film transistor and manufacturing method thereof, array substrate

The present disclosure provides a thin film transistor, a method for manufacturing the same, an array substrate and a display device. The method for manufacturing a thin film transistor includes providing a substrate, forming a gate electrode, a gate insulating layer, an amorphous silicon material active layer and a cap layer on the substrate successively, wherein The cap layer is provided with a pattern on a side of the cap layer away from the amorphous silicon material active layer, and the pattern is composed of at least one groove along a length direction of the active layer and at least one groove along a width direction of the active layer, subjecting the amorphous silicon material active layer to laser annealing treatment to transform the amorphous silicon material active layer into a low temperature polycrystalline silicon material active layer, and removing the cap layer.

Thin film transistor, method for manufacturing the same, array substrate and display device

A display panel which includes a display area and a peripheral area around the display area is provided. The peripheral area includes an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines. The electroluminescent layer test region includes a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers. The TFT test region includes a plurality of thin film transistors. Each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.

Display panel and a manufacturing method thereof, a TFT test method

An array substrate, a manufacturing method thereof and a display apparatus are provided. The array substrate includes thin-film transistors (TFTs) and conductive electrodes; the TFT includes a gate electrode, a source electrode, a drain electrode and an active layer; the source electrode and the drain electrode are arranged in the same layer and at two ends of the active layer and at least directly partially contact the upper surface or the lower surface of the active layer; and the conductive electrode is directly disposed on the electrode. With improved layer structures of the array substrate, a plurality of layer structures is formed in one patterning process by stepped photoresist process, so as to reduce the frequency of patterning processes, better ensure the compactness of the array substrate, and guarantee good contact between the layer structures in the array substrate.

Array substrate manufactured by reduced times of patterning processes manufacturing method thereof and display apparatus

The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.

Low temperature polycrystalline silicon TFT array substrate and method of producing the same, display apparatus

The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.

Method for manufacturing thin film transistor and related active layer for thin film transistor, thin film transistor, array substrate, and display apparatus

Embodiments of the present invention disclose a manufacturing method of a thin film transistor, a thin film transistor, an array substrate and a display device. The manufacturing method of a thin film transistor includes a step of forming an active layer, and the step of forming an active layer includes: forming a first poly-silicon layer and a second poly-silicon layer on the first poly-silicon layer separately, and adding dopant ions into the second poly-silicon layer and an upper surface layer of the first poly-silicon layer. By using the manufacturing method of a thin film transistor, defect states and unstable factors of interface in the thin film transistor can be reduced, thereby improving stability of the LTPS thin film transistor and obtaining an array substrate and a display device having more stable performance.

Thin film transistor, manufacturing method thereof, array substrate, and display device

The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other. The passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein. The first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.

Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device

A thin-film transistor (TFT), a manufacturing method thereof, display substrate and a display device are disclosed. The TFT includes: an active layer, gate insulating layer, gate electrode, interlayer dielectric layer, source electrode and a drain electrode disposed on a base substrate in sequence. The source electrode and drain electrode are respectively connected with the active layer via a through hole exposing the active layer; the gate insulating layer at least includes a silicon oxide layer and a silicon nitride layer in a two-layer structure; the interlayer dielectric layer at least includes silicon oxide layers and silicon nitride layers in a four-layer structure; the silicon oxide layers and silicon nitride layers of the gate insulating layer and the interlayer dielectric layer are alternately arranged; and the dimension of one side of the through hole away from the base substrate is greater than that of one side close to the base substrate.

Thin-film transistor, manufacturing method thereof, display substrate and display device

An annealing apparatus includes: a temperature-gradient preheating unit, configured for performing a gradient-preheating process for a substrate that is to be annealed by using a gradient temperature; a high temperature heating unit, configured for performing a high temperature heating process for the preheated substrate; and a shifting device, configured for transporting the substrate from the temperature-gradient preheating unit to the high temperature heating unit when and/or after the substrate is subjected to the gradient-preheating process. The annealing apparatus adopts a gradient heating method to perform a preheating treatment for the substrate, so the annealing efficiency is increased. An annealing process that uses the annealing apparatus is further provided.

Annealing apparatus and annealing process

The embodiments of the present invention provide a thin film transistor driving backplane and a manufacturing method thereof, and a display panel. The manufacturing method may comprise: manufacturing a backplane base disposed with a plurality of active device structures; disposing an electrode layer on the backplane base; and manufacturing the electrode layer into a source electrode, a drain electrode and a pixel electrode integrally disposed with the drain electrode by one patterning process. According to the embodiment of the present invention, the electrode layer is manufactured into a plurality of source electrodes, drain electrodes and pixel electrodes, integrally disposed with the drain electrode, by one time patterning process, so that the source electrode, the drain electrode and the pixel electrode are all at the same electrode layer, and the source electrode, the drain electrode and the pixel electrode whose formation needs two patterning processes in the existing method, is simplified to one time patterning process, so it reduces the thickness of the thin film transistor driving backplane, simplifies the manufacturing step, and saves the manufacturing cost.

Growing community of inventors

Beijing, China

Zuqiang Wang