Shenzhen Microbt Electronics Technology Co., Ltd.

Zuoxing Yang

Haifeng Guo

Zhijun Fan

Yuefeng Wu

Lihong Huang

Weibin Ma

Yang Gao

Wenbo Tian

Weixin Kong

Chao Xu

Dong Hai Yu

Guo Ai

Ke Xue

Qian Chen

Nan Li

Jianbo Liu

Hongyan Ning

Zhihong Xiang

Ruming Fang

Danyang Wang

Yun Zhai

Fangyu Liu

Chuan Gong

Hong Zhang

Tianzhi Xue

Jianli Wei

Sibin Gao

Chengtao Zhou

Le Zhang

Zhongping Wang

Ju He

Shuangyan Chen

The present disclosure relates to a phase-locked loop circuit and a signal processing device. The phase-locked loop circuit includes: a charge pump configured with a charge pump current; and a loop filter connected to the charge pump and configured with a first resistance value, a first capacitance value, and a second capacitance value, wherein a zero frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the first capacitance value, and a pole frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the second capacitance value; wherein at least two of the charge pump current, the first resistance value, the first capacitance value, and the second capacitance value are adjustable, to change a loop bandwidth of the phase-locked loop circuit, to maintain a first ratio between the zero frequency and the loop bandwidth unchanged, and to maintain a second ratio between the pole frequency and the loop bandwidth unchanged.

Phase-locked loop circuit and signal processing device

The present application relates to a supercomputing server including: a case housing defining an accommodating space and provided with a mounting hole allowing communication between the accommodating space and an external environment; and a control unit disposed at an end portion of the case housing corresponding to the mounting hole and configured to be moved into or out of the accommodating space through the mounting hole. After the control unit is disassembled from the case housing, the control unit may be moved out of the accommodating space through the mounting hole at the end portion of the case housing to maintain the control unit. After the maintenance, the control unit is moved into the accommodating space through the mounting hole, and the control unit is fixed at the end portion of the case housing.

Supercomputing server

Embodiments of this application provide a chip frequency control method and apparatus, a blockchain server, and a storage medium. The method includes: determining a real-time computing power ratio of a chip of a blockchain server, a real-time temperature of the chip, and a real-time voltage of the chip; and adjusting a setting frequency of the chip based on a first comparison result of the real-time computing power ratio with a reference computing power ratio of the chip, a second comparison result of the real-time temperature with a reference temperature of the chip, and a third comparison result of the real-time voltage with a reference voltage of the chip, wherein the reference computing power ratio, the reference temperature, and the reference voltage are determined when the blockchain server undergoes a frequency rising phase after start-up and enters a working status. When an exception occurs in the chip, timely and appropriate response can improve stability of the blockchain server.

Chip frequency control method and apparatus, blockchain server, and storage medium

The present disclosure relates to a multiplier, a multiply-accumulate circuit, an operational circuit, a processor, and a calculation apparatus. The operational circuit includes an input processing circuit and the multiply-accumulate circuit. The input processing circuit receives a first number and outputs the first number as a first multiplicator for feeding into the multiply accumulate circuit by negating a sign bit of the first number in a case in which the first number is a signed number, and directly outputs the first number as the first multiplicator for feeding into the multiply-accumulate circuit in a case in which the first number is an unsigned number. The input processing circuit further receives a previously known second number and directly outputs the second number as a second multiplicator for feeding into the multiply-accumulate circuit. The multiply-accumulate circuit includes a multiplication subcircuit and an accumulation subcircuit.

Multiplier, multiply-accumulate circuit, operational circuit, processor, and calculation apparatus

The present disclosure relates to a multiplier, a multiply-accumulate circuit, and a convolution operation unit. The multiplier includes: one or more selection circuits, each of the one or more selection circuits respectively configured to select a target preset multiple of a first operand from a preset multiple of a first operand as a fourth operand according to a corresponding third operand, wherein the target preset multiple is equal to a value of the third operand; and a partial product summing circuit, each of one or more input terminals of the partial product summing circuit respectively connected to an output terminal of corresponding one of at least one or more selection circuits, wherein the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits.

Multiplier, multiply-accumulate circuit, and convolution operation unit

The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.

D flip-flop having multiplexer function

Disclosed include a data collection device, a data collection system, and an electronic image stabilization device. The data collection device includes a logic circuit. The logic circuit includes: a timer, configured to generate timestamp data; a control module, configured to, in response to receiving a pre-set input signal, generate a data obtaining command and obtain the timestamp data from the timer; a communication module, configured to, in response to the data obtaining command, obtain MEMS (MEMS) data from a MEMS sensor; and a packing module, configured to pack the MEMS data and the timestamp data into a data packet.

Data collection device, data collection system, and electronic image stabilization device

A resonant tank circuit includes: a number-of-turns variable transformer unit, having an input end coil and an output end coil, the input end coil including at least two first connection ends and a second connection end, where a number of coil turns between each of the first connection ends and the second connection end is not equal; a switch switching unit, having a control end, a first input end, and at least two first output ends, where a quantity of the first output ends is equal to a quantity of the first connection ends, the first output ends are electrically connected to the first connection ends in a one-to-one manner, and the switch switching unit is configured to turn on a circuit connection between the first input end and one of the at least two first output ends according to a control signal received by the control end.

Resonant tank circuit, wide voltage input/output power supply, and electronic device

A method and an apparatus for generating a video digest, and a readable storage medium are provided. The method is applied to a video acquisition device that includes a hardware unit configured to obtain movement information in real time, the movement information includes speed information and direction information of the video acquisition device. The method includes: starting acquisition of a video signal in response to an acquisition start instruction, and recording movement information corresponding to each frame during the acquisition of the video signal; determining a frequency for key frame extraction according to the movement information corresponding to each frame; determining a key frame from the acquired video signal according to the frequency for key frame extraction; and in response to an acquisition end instruction, generating a video digest according to the key frame.

Method and apparatus for generating video digest and readable storage medium

This disclosure relates to a divider, a processor, and a calculation apparatus. The divider includes: a first-stage shift circuit, configured to shift a received first operand to left to generate a second operand; a first-stage selection circuit, configured to select a first preset multiple of a third operand as a fourth operand from preset multiples of the third operand; and a first-stage operational circuit, configured to calculate an OR operation result of the first preset multiple and a difference between the second operand and the fourth operand as a fifth operand.

Divider, processor, and calculation apparatus

A dynamic D flip-flop with an inverted output involves an input end () used for receiving input data; an output end () used for providing output data to respond to the input data; a clock signal end () used for receiving a clock signal; a first latch () used for latching the input data from the input end () and performing inverting transmission on the input data under the control of the clock signal; a second latch () used for latching data from the first latch () and performing inverting transmission on the data latched by the first latch () under the control of the clock signal; and an inverter () used for performing inverting output on the data received from the second latch (), the first latch (), the second latch (), and the inverter () being sequentially connected in series between the input end and the output end.

Dynamic D flip-flop with an inverted output

The present disclosure relates to clock circuits, computing chips, hash boards and data processing devices. A clock circuit comprises M stages of clock drive circuits that are connected in series, M being an integer that is no less than 2, wherein N inverters connected in series are arranged between an input port and an output port of each stage of the M stages of clock drive circuits, N being an odd number that is no less than 3. The clock circuit may provide clock signals with excellent performance.

Clock circuits, computing chips, hash boards and data processing devices

A D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.

D flip-flop, processor including the d flip-flop, and computing apparatus

The present disclosure is directed to a series-connected power supply circuit and a data processing device. The series-connected power supply circuit comprises: at least two layers of to-be-powered chips (A, A, . . . , Am) connected in series between a first power supply end (A) and a second power supply end (B), with a highest-layer to-be-powered chip (Am) in the at least two layers of to-be-powered chips (A, A, . . . , Am) connected to the first power supply end (A), and a bottommost-layer to-be-powered chip (A) in the at least two layers of to-be-powered chips (A, A, . . . , Am) connected to the second power supply end (B); and each layer of auxiliary power supply units (B, B, . . . , Bm), which is respectively connected to each layer of the to-be-powered chips (A, A, . . . , Am), wherein the first power supply end (A) is configured to receive a reference voltage.

Layered series-connected power supply circuit and data processing device for supplying power to computing chips connected in series from bottommost layer to highest layer

An electronic device includes an arithmetic unit layer and a power supply. The arithmetic unit layer comprises at least one arithmetic unit. Each arithmetic unit comprises a first housing in a shape of cuboid. A first side direction of the first housing extends in a first direction. The first housing is provided with first and second openings at both ends in the first side direction thereof to form a coolant passage extending in the first direction. The power supply is stacked with arithmetic unit layer in a second or a third direction. A first side direction of the power supply is aligned with the first side direction of each arithmetic unit. The power supply is provided with third and fourth openings at both ends in the first side direction thereof to form a coolant passage extending in the first side direction of the power supply.

Growing community of inventors

Guangdong, China

Zuoxing Yang