International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Elpis Technologies Inc.

Zuoguang Liu

Tenko Yamashita

Chun-chen Yeh

Veeraraghavan S Basker

Kangguo Cheng

Dechao Guo

Heng Wu

Oleg Gluschenkov

Chia-Yu Chen

Shogo Mochizuki

Praneet Adusumilli

Xin Miao

Hiroaki Niimi

Ruilong Xie

Peng Xu

Juntao Li

Sanjay C Mehta

Chun Wing Yeung

Chen Zhang

Miaomiao Wang

Ruqiang Bao

Wenyu Xu

Su Chen Fan

Gen Tsutsui

Sebastian Naczas

Rajasekhar Venigalla

Jie Yang

Alexander Reznicek

Junli Wang

Hemanth Jagannathan

Chung-Hsun Lin

Huiming Bu

Arthur Gasasira

Joseph S Washington

Jiseok Kim

Brent A Anderson

Carl John Radens

Oscar Van Der Straten

Muthumanickam Sankarapandian

Chun-Chen Yeh

Huimei Zhou

Richard Glen Southwick, Iii

Xin Sun

A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

Phase change memory with conductive rings

A phase change memory includes a substrate, a plurality of first phase change elements on the substrate, a plurality of electrodes on the plurality of first phase change elements, and a second phase change element connecting the plurality of electrodes and disposed between the plurality of first phase change elements.

Reducing contact resistance of phase change memory bridge cell

A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Punch through stopper in bulk finFET device

Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

Layout design for threshold voltage tuning

Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5&#xd7;10atoms per cubic centimeter (at./cm). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

Low resistance source drain contact formation with trench metastable alloys and laser annealing

A phase change memory (PCM) cell includes a first electrode, a heater electrically connected to the first electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, and a resistive liner in direct contact with and electrically connected to a sidewall of the heater and to the PCM material.

Phase change memory cell resistive liner

A semiconductor structure including a bottom source drain region arranged on a substrate, a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region, a metal gate disposed on and around the semiconductor channel region, and a top source drain region above the semiconductor channel region and comprising a first doped epitaxy region and a second doped epitaxy region.

Two-stage top source drain epitaxy formation for vertical field effect transistors enabling gate last formation

Self-aligned gate/junction for VTFET devices are provided. In one aspect, a method of forming a VTFET device includes: forming a stack on a wafer including a first c-SiGe layer, a c-Si layer, and a second c-SiGe layer, wherein the first c-SiGe layer serves as a bottom source/drain; forming fin hardmasks on the stack; partially recessing the second c-SiGe layer to form a fin(s) in the second c-SiGe layer, wherein the second c-SiGe layer that is partially recessed/fin(s) serve as a top source/drain; amorphizing the c-Si layer to form a-Si regions in between c-Si regions that serve as vertical channels; selectively removing the a-Si regions to form gate trenches; forming bottom/top spacers in the gate trenches; and forming gates in the gate trenches that are offset from the bottom/top source/drain by the bottom/top spacers. A VTFET device is also provided. The VTFET device is suitable for 3D monolithic integrated circuits.

Self-aligned gate and junction for VTFET

Devices and methods are provided for fabricating shared contact trenches for source/drain layers of n-type and p-type field-effect transistor devices, wherein the shared contact trenches include dual silicide layers and dual epitaxial layers. For example, a semiconductor device includes first and second field-effect transistor devices having respective first and second source/drain layers, and a shared contact trench, wherein the first and second source/drain layers are disposed adjacent to each other within the shared contact trench, and are commonly connected to each other by the shared contact trench. The shared contact trench includes a first silicide contact layer disposed on the first source/drain layer, and a second silicide contact layer disposed on the second source/drain layer, wherein the first and second silicide contact layers comprise different silicide materials, and a metallic fill layer disposed on the first and second silicide contact layers.

Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices

A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.

Composite spacer enabling uniform doping in recessed fin devices

Semiconductor device structures and techniques are provided for measuring contact resistance. A semiconductor device is disclosed including a first source/drain region and a contact disposed on the first source/drain region and configured to supply energy to the semiconductor device. A fin extends between the first source/drain region and a second source/drain region of the semiconductor device. A first contact material layer is disposed on the second source/drain region and a first active drain contact is disposed on the first contact material layer. A first sensor drain contact is also disposed on the first contact material layer. A second contact material layer is disposed on the second source/drain region and a second active drain contact is disposed on the second contact material layer. A third contact material layer is disposed on the second source/drain region and a second sensor drain contact is disposed on the third contact material layer.

Measurement of top contact resistance in vertical field-effect transistor devices

A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar.

Vertical field effect transistor replacement metal gate fabrication

The present invention provides VFET device designs for top contact resistance measurement. In one aspect, a method of forming a VFET test structure includes: etching fins in a substrate (for active and sensing devices); forming bottom source/drains at a base of the fins; forming a STI region that isolates the bottom source/drains of the active device from that of the sensing device; forming a gate surrounding each of the fins; forming top source/drains over the gate, wherein the top source/drains of the active device and that of the sensing device are merged; and forming contacts to i) the bottom source/drains of the active device, ii) the top source/drains of the active device, and iii) the bottom source/drains of the sensing device. A test structure formed by the method as well as techniques for use thereof for measuring contact resistance are also provided.

VFET device design for top contact resistance measurement

A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on a substrate, forming at least two vertical fins on the bottom source/drain region, forming a protective spacer on the at least two vertical fins, forming a sacrificial liner on the protective spacer, forming an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins, forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and forming the dielectric separator on the insulating plug.

Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap

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Schenectady, NY, United States of America

Zuoguang Liu