Cypress Semiconductor Corporation

Spansion Llc.

Piquant Research LLC

Zubin Patel

Fei Wang

Angela Tai Hui

Calvin T Gabriel

Shenqing Fang

Mark S Chang

Alexander H Nickel

Minh-Van Ngo

Jihwan Choi

Phillip Lawrence Jones

Alok Nandini Roy

Nian Niles Yang

Hidehiko Shiraiwa

Gulzar Ahmed Kathawala

Wai Lo

Arun Ramamoorthy

Fan Wan Lai

Tracy Helen Fung

Jinsong Tang

A shallow bipolar junction transistor comprising a high voltage n+ well implanted into a semiconductor substrate. The shallow bipolar junction transistor further comprises a bit line n+ implant (BNI) above the high voltage n+ well and an oxide nitride (ONO) layer above the high voltage n+ well. A portion of the ONO layer isolates the BNI from a shallow trench isolation (STI) region.

Shallow bipolar junction transistor

A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer. The substrate intermediate layer and the device intermediate layer comprise a distribution in their compositions along a thickness coordinate.

Defect mitigation structures for semiconductor devices

A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.

System and method for multi-layer global bitlines

A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications

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San Jose, CA, United States of America

Zubin Patel