National Instruments Corporation

Zu-Yi Wang

Joseph E Peck

Kosta Ilic

Jaffar Shah

A latency error detection circuit including two cascaded latches receiving a clock signal from a measuring system upon the occurrence of an event and correspondingly asserting a bit to a processing system, and a circuit for clearing the first latch after the processing system acknowledges detecting the bit being asserted. If the second latch is clocked before the first latch is cleared, the second latch sets an error bit indicating a latency error condition. The processor system monitors the error bit to determine whether a latency error has occurred.

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Travis County, TX, United States of America

Zu-Yi Wang