International Business Machines Corporation

Zu-Jean Tien

Louis L Hsu

David Edward Kotecki

Jeffrey P Gambino

Jack Oon Chu

Seshadri Subbanna

Chang-Ming Hsieh

Christopher Carr Parks

Brian Cunningham

Jeffrey L Blouse

Shantha A Kumar

Jerzy Kanicki

Shwu Jen Jeng

A polyemitter structure having a thin interfacial layer deposited between the polysilicon emitter contact and the crystalline silicon emitter, as opposed to a regrown SiO.sub.x layer, has improved reproducibility and performance characteristics. A n-doped hydrogenated microcrystalline silicon film can be used as the deposited interfacial film between a crystalline silicon emitter and a polycrystalline silicon contact.

Polyemitter structure with improved interface control

A method of manufacturing a bipolar transistor by use of low temperature emitter process is disclosed. After completion of the usual base and collector formation in a vertical bipolar transistor, an emitter opening is etched in the insulator layer over the base layer at selected locations. A thin layer (less than 500 .ANG.) of in-situ doped amorphous silicon is deposited over the substrate and heated to densify for 30 to 60 minutes at about 650.degree. C. Subsequently an in-situ doped polysilicon layer of 100 to 200 nm is deposited over the amorphous Si film preferably at about 600.degree. C. Subsequently the layers are heated below 600.degree. C. for several hours to convert partially the amorphous Si into a monocrystalline emitter layer over the base regions.

Low temperature emitter process for high performance bipolar devices

A method of forming a semiconductor structure comprising the steps of: providing a body of semiconductor material including at least one generally planar surface; forming a mesa having at least one generally vertical wall over the planar surface; forming a layer of material generally conformally over the mesa and the planar surface so as to form a vertical spacer on the vertical wall; forming a protective mask selectively on the upper portion of the vertical spacer; and using the protective mask to etch and remove the unmasked portions of the layer of material and the mesa while leaving the vertical spacer. The process is used to form an FET by forming a gate insulating layer underneath of the vertical spacer, the vertical spacer being selected to comprise a conductive gate material such as doped polysilicon. The vertical gate structure is then used as a mask to dope the source and drain regions.

Field effect transistor formed with deep-submicron gate

An apparatus and method for monitoring a change of thickness of a first material with a first bandgap energy, for disposal over a second material on a wafer and having a second different bandgap energy, wherein at least one of the materials has a direct bandgap. The apparatus comprises means for changing the thickness of the first material layer; means for directing a beam of energy to impinge at an angle on to the surface and to penetrate the wafer, with the beam having an energy sufficient to pump the at least one direct bandgap material to a higher energy state; and means for detecting the induced luminescence from the at least one direct bandgap material to determine when to alter the thickness changing process. The present invention may be used to monitor both deposition and etching processes. It is particularly suited for determining the etch endpoint for III-V semiconductor materials such as GaAs and AlGaAs.

Laser luminescence monitor for material thickness

Growing community of inventors

Saratoga, CA, United States of America

Zu-Jean Tien