Imec Vzw

Taiwan Semiconductor Manufacturing Comp. Ltd.

Imec

Zsolt Tokei

Chao Zhao

Boon Teik Chan

Christopher Wilson

Juergen Boemmels

Soeren Steudel

Basoene Briggs

Julien Ryckaert

Vladimir Machkaoutsan

Paul Heremans

Hans Mertens

Jan Genoe

Stefan Cosemans

Naoto Horiguchi

Gerald Beyer

Martin O'Toole

Sven Van Elshocht

Steven Demuynck

Marc Schaekers

Antony Premkumar Peter

Ryan Ryoung Han Kim

Anna Yurievna Herr

Quentin Paul Herr

Roger Palmans

Anshul Gupta

Serge Biesemans

Stefan Decoster

Katia Devriendt

Laure Elisa Carbonell

Yu Chen-Hua

Farid Sebaai

Bilal Chehab

Chung-Shi Liu

Martin O´TOOLE

A method for forming a superconducting interconnect structure, comprising: providing a substrate, forming a superconductive layer, forming a layer of a first dielectric material, removing parts of the layer of the first dielectric material and of the superconductive layer so as to form a pattern comprising a first set of line structures comprising: a first set of superconductive line structures, and a first set of line structures made of the first dielectric material, forming a second dielectric material between the line structures of the first set, forming a layer formed of a third dielectric material, providing a patterned mask, transferring the pattern into the first dielectric material and into the layer formed of the third dielectric material, so as to form the at least one via hole, removing the patterned mask, and forming a superconductive material layer so as to form at least one via.

Superconductive interconnect structure

Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend.

Integrated circuit with an interconnection system having a multilevel layer providing multilevel routing tracks and method of manufacturing the same

Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.

Method for forming a via hole self-aligned with a metal block on a substrate

A method is provided for producing electrically conductive lines (), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.

Semiconductor fabrication method for producing nano-scaled electrically conductive lines

A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

Method of forming a multi-level interconnect structure in a semiconductor device

A Light Emitting Diode (LED) device, particularly a micro-LED (&#x3bc;LED) device, suitable for a &#x3bc;LED display is described. The LED device comprises a LED array with a plurality of LEDs. It also comprises at least one top contact and bottom contact electrically connected to the LED array. Further, it comprises a conductive structure arranged above the LED array and the top contact, respectively, and electrically connected to the top contact. The conductive structure is, regarding each LED of the LED array, configured to absorb a first part of the light emitted by the LED, and to pass a second part of the light emitted by the LED. An emission angle (beam angle) of the passed light is thereby smaller than an emission angle of the light emitted by the LED.

Apex angle reduction in a LED device with a LED array

The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.

Method of patterning target layer

Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

Method for manufacturing germamde interconnect structures and corresponding interconnect structures

An interconnect structure and a method for forming it is disclosed. In one aspect, the method includes the steps of providing a first entity. The first entity includes a first set of line structures. The first set of line structures include a first set of conductive lines, and a first set of dielectric lines made of a first dielectric material and aligned with and overlaying the first set of conductive lines. The first entity also includes gaps separating the line structures and filled with a second dielectric material of such a nature that the first dielectric material can be selectively etched with respect to the second dielectric material. The method also includes providing a patterned mask on the first entity. The method further includes etching selectively the first dielectric material through the patterned mask so as to form one or more vias in the first dielectric material. The method also includes removing the patterned mask.

Self-aligned interconnects

A Field-Programmable Gate Array device is provided with programmable interconnect points in the form of interconnect circuits comprising one or more pass transistors, wherein at least some components of the interconnect circuits are implemented in the Back-End-Of-Line part of the Field-Programmable Gate Array device's production process. The memory element in an interconnect point is not produced as a Static Random Access Memory cell, but as a Dynamic Random Access Memory cell, requiring only a single select transistor and a storage capacitor for each memory element. The fabrication of at least the select transistor and the pass transistor involves the use of a thin film semiconductor layer, e.g., Indium Gallium Zinc Oxide, enabling production of transistors with low leakage in the Back-End-Of-Line.

Filed programmable gate array device with programmable interconnect in back end of line portion of the device

Growing community of inventors

Leuven, Belgium

Zsolt Tokei