Stmicroelectronics S.r.l.

Zsolt Miklos Kovacs-Vajna

Luigi Colalongo

Anna Richelli

Luca Mensi

Marco Pasotti

Davide Lena

Fabrizio Torricelli

Giancarlo Pisoni

An embodiment of non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory includes at least one sector of a plurality of memory cells; each sector includes a storage region of a first type of conductivity and a further storage region of a second type of conductivity. Each memory cell includes a first region and a second region of the second type of conductivity, which are formed in the storage region for defining a storage transistor of floating gate MOS type of the first type of conductivity; the memory cell likewise includes a further first region and a further second region of the first type of conductivity, which are formed in the further storage region for defining a further storage transistor of floating gate MOS type of the second type of conductivity. The memory cell also includes a common floating gate of the storage transistor and the further storage transistor. The memory device further includes programming means for programming each memory cell individually by programming the corresponding floating gate through the corresponding storage transistor, and erasing means for erasing each memory cell individually by erasing the corresponding floating gate through the corresponding further storage transistor.

FTP memory device programmable and erasable at cell level

A two-phase charge pump is provided that is capable of being controlled by first and second clock signals that are out-of-phase and take alternatively a first value and a second value during consecutive phases. The charge pump includes a sequence of cascade-connected stages that each have a first section and a second section. Each section includes an input terminal and an output terminal, a capacitive element, and a controlled switch coupling the input terminal of the section with the output terminal of the section. The input terminals in each stage other than the first stage are cross-coupled with the output terminals in a preceding stage. The capacitive element has first and second terminals. The first terminals in the first and second sections receive the first and second clock signals, respectively, and the second terminal is coupled with the output terminal of the section. The controlled switch has a control terminal. In each stage, the control terminals are coupled to each other. The first section further includes a first control circuit coupling the control terminal with the output terminal of the first section during the first phase, and the second section further includes a second control circuit coupling the control terminal with the input terminal of the second section during the second phase.

Charge pump circuit with reuse of accumulated electrical charge

A two-phase charge pump is provided that is controlled by first and second clock signals in phase-opposition. The charge pump has a sequence of cascade-connected stages. Each stage includes a capacitive element driven by one clock signal such that capacitive elements of adjacent stages are driven by different clock signals, a pass transistor that transfers electric charge to the capacitive element from the capacitive element of a previous stage, a first biasing circuit that enables the pass transistor during a first phase of the one clock signal, and a second biasing circuit that disables the pass transistor during a second phase of the one clock signal. Also provided is a two-phase charge pump having two branches that each include a sequence of such cascade-connected stages, with each stage of one branch having a corresponding stage in the other branch. A method of operating two-phase charge pumps is also provided.

Charge pump circuit with dynamic biasing of pass transistors

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Concesio, Italy

Zsolt Miklos Kovacs-Vajna