Stmicroelectronics S.r.l.

Zsolt M Kovacs

Michele Borgatti

Filippo Mondinelli

A network, such as a network on chip, includes a plurality of levels of switches organized in a hierarchy. The connections between the switches are constituted by connections which are able to transport packets of information in opposite directions in such a way that one switch, or one process associated thereto, can send or receive packets in the framework of the network along one and the same path, constituted by an ascending stretch, in which the packet goes up the network hierarchy as far as a root switch common to the source and to the destination, and a descending stretch in which the packet goes down the network hierarchy towards the destination. A routing logic is provided, configured for defining the routing path in a non-adaptive way, selecting the ascending stretch according to the source and the descending stretch according to the destination, irrespective of the traffic of the packets.

Routing procedure and system, corresponding network, such as a network on chip (NOC), and computer program product therefor

An alphanumeric character image recognition system includes a first stage comprising at least a first, second and third digital image signal processing network having each at least one input terminal and at least one output terminal and said networks being designed to process image information from digital image signals, and comprising at least a first, second and third memory register having each at least one input terminal and at least one output terminal and the input terminals of the first, second and third memory registers being connected to the output terminal of the first network, the output of the second network and the output terminal of the third network respectively and said memory registers being designed to contain the image information processed by the first, second and third digital image signal processing networks, and a second stage characterized in that said second stage comprises at least one first and one second classifier network having each at least one first and one second input terminal and a plurality of output terminals, the first input terminal of the first classifier network being connected to the output terminal of the first memory register and the second input terminal of said first classifier network being connected to the output terminal of the second memory register and the first input terminal of the second classifier network being connected to the output terminal of the second memory register and the second input terminal of said second classifier network being connected to the output terminal of the third memory register and at least one third classifier network having a plurality of input terminals connected to a plurality of output terminals of the first and second classifier networks and a plurality of output terminals which are output terminals of the system and said classifier networks being designed to carry out consecutive statistical operations on the image information until there are obtained statistical values corresponding to a predetermined classification of images to be recognized.

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Bologna, Italy

Zsolt M Kovacs