Intel Corporation

Nxp B.v.

Ams International Ag

Zoran Zivkovic

Kameran Azadet

Feike Guus Jansen

Kannan Rajamani

Thomas Smith

Javier Perez-Ramirez

Kim Phan Le

Joseph Williams

Gilad Michael

Hilco Suy

Aleksandar Sutic

Kevin Kinney

Spencer Markowitz

Michael E Kounavis

Richard D Roberts

Youri Victorovitch Ponomarev

Willem Frederik Adrianus Besling

Frank Leong

Alessio Filippi

Casper Van Der Avoort

Jian-Guo Chen

Antonius Johannes Matheus De Graauw

Stefan Drude

Jan Rene Brands

Edwin Jan Van Dalen

Marc Vauclair

Coenraad Cornelis Tak

Aleksandar Beric

Nebojsa Nenadovic

Timo Van Roermund

Lukasz Szostek

Jan René Brands

Kari Pulli

Frank Harald Erich Ho Chung Leong

Christophe Macours

Rufeng Meng

Ankitkumar Pravinbhai Navik

Liang Li

Jay O'Neill

Barry De Bruin

Gregoire Kerr

Nagarajan Muralidharan

Hong Wan

David Dougherty

Martin Valkenburg

Christophe Marc Macours

Nemanja Jankovic

Franciscus Petrus Widdershoven

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.

Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

Digital pre-distortion (DPD) adaptation using a hybrid hardware accelerator and programmable array architecture

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

Hybrid hardware accelerator and programmable array architecture

Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

Vector processor utilizing massively fused operations

Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.

Vector processor supporting linear interpolation on multiple dimensions

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.

Multicore synchronization mechanism for time critical radio systems

Systems, devices, and techniques related to selecting a key frame for burst image processing are discussed. Such techniques may include generating key frame scores for at least some frames of a multi-frame burst image capture such that the key frame scores include a combination of an image quality component, a shutter lag component, and a burst image processing latency component and selecting a frame having a maximum key frame score as the key frame.

Key frame selection in burst imaging for optimized user experience

An apparatus and method for performing multiply-accumulate (MAC) operations on complex numbers to generate real results. For example, one embodiment of a processor comprises: a decoder to decode instructions including multiply-accumulate instructions; first and second source registers to store a first plurality of complex values and a second plurality of complex values, respectively, each complex value comprising a real value and an imaginary value; multiply-accumulate (MAC) execution circuitry coupled to the first and second source registers comprising multiplier circuitry, adder circuitry, and accumulator circuitry; mode selection circuitry to select between at least two execution modes for the MAC execution circuitry including a first mode in which the MAC execution circuitry is to perform complex multiply-accumulate operations using real and imaginary values from the first plurality of complex values and the second plurality of complex values and a second mode in which the MAC execution circuitry is to replace one or more of the real or imaginary values from the first and second plurality of complex values with one or more real or imaginary values specified in a set of scalar complex numbers or with zeroes.

Apparatus and method for controlling complex multiply-accumulate circuitry

In an example method for training image signal processors, a reconstructed image is generated via an image signal processor based on a sensor image. An intermediate loss function is generated based on a comparison of an output of one or more corresponding layers of a computer vision network and a copy of the computer vision network. The output of the computer vision network is based on the reconstructed image. An image signal processor is trained based on the intermediate loss function.

Training image signal processors using intermediate loss functions

In one embodiment, an apparatus comprises an antenna to receive one or more radio signals, wherein the antenna is associated with a proximity-based access portal. The apparatus further comprises a processor to: detect, based on the one or more radio signals, an access request from a first device, wherein the access request comprises a request to access the proximity-based access portal using an access token associated with an authorized device; determine, based on the one or more radio signals, that the first device is within a particular proximity of the proximity-based access portal; obtain a first motion history associated with movement detected near the proximity-based access portal; obtain a second motion history associated with movement detected by the authorized device; and determine, based on the first motion history and the second motion history, whether the movement detected near the proximity-based access portal matches the movement detected by the authorized device.

Surveillance-based relay attack prevention

An integrated temperature sensor comprises a chip package enclosing an integrated circuit and an ultrasonic transceiver which is integrated on top of the integrated circuit. The ultrasonic transceiver comprises a transmitting element which is arranged for emitting ultrasound waves, and a receiving element which is arranged for receiving ultrasound waves. The chip package comprises at least one barrier arranged at a defined position in the chip package. The barrier is designed to at least partly reflect ultrasound waves emitted by the transmitting element towards the receiving element. The integrated circuit comprises an actuator element to actuate the transmitting element to emit ultrasound waves according to a first signal s(t), and a converter element to convert an ultrasound wave, received by the receiving element, into a second signal y(t). Furthermore, a method for producing an integrated temperature sensor and a method for determining a temperature by means of an integrated temperature sensor are presented.

Integrated temperature sensor, method for producing an integrated temperature sensor and method for determining a temperature by means of an integrated temperature sensor

A method, system, and article is directed to geolocation and attitude correction for mobile rolling shutter cameras.

Method and system of geolocation and attitude correction for mobile rolling shutter cameras

This disclosure describes systems, methods, and devices related to frequency offset tracking in optical signals. A device may identify modulated light received from a light source, wherein the modulated light is received at a frame rate, and wherein the modulated light is associated with pixel clusters. The device may determine light samples based on the pixel clusters, the light samples including a first light sample and a second light sample. The device may determine a vector norm between the first light sample and the second light sample using an oversampling factor. The device may determine that the vector norm is below a threshold. The device may determine a start frame delimiter (SFD) based on the vector norm. The device may demodulate the symbol based on the oversampling factor.

Enhanced frequency offset tracking in optical signals

An apparatus and method for performing FIR filtering and blending operations. A processor comprising: a decode unit to decode a packed N-tap finite impulse response (FIR) filter instruction, the packed N-tap FIR filter instruction to indicate one or more source packed data operands comprising a plurality of packed data elements, at least 3 filter coefficients, and a destination storage location, the plurality of packed data elements comprising data from a signal to be filtered and the plurality of filter coefficients specifying a filter function to be applied; and an execution unit comprising an FIR unit coupled with the decode unit, the FIR unit, in response to the packed N-tap FIR filter instruction being decoded by the decode unit, to perform at least N&#x2212;1 multiplications to generate at least N&#x2212;1 products, each of the multiplications comprising one of the filter coefficients multiplied by one of the packed data elements, the execution unit to combine the at least N&#x2212;1 products in accordance with a specified type of FIR filter being implemented to generate a result packed data element to be stored in the destination storage location.

Apparatus and method for performing horizontal filter operations

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Hertogenbosch, Netherlands

Zoran Zivkovic