Oracle International Corporation

Sun Microsystems, Inc.

Oracle America, Inc.

Zoran Radovic

Paul N Loewenstein

Erik Hagersten

John Johnson

Darryl J Gove

Graham Ricketson Murphy

Paul Joseph Jordan

Robert Cypher

Shailender Chaudhry

Robert T Golla

Lawrence Spracklen

John Robert Rose

Erik E Hagersten

Mark Luttrell

Anders Landin

Sanjiv Kapil

Kathirgamar Aingaran

Bharat Daga

Jared Smolens

Jonathan William Adams

Håkan E Zeffer

Erik Martin Roland Karlsson

Oskar Grenholm

Paul Loewenstein

A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory. To maintain memory coherency, a memory coherence protocol is implemented. Under this protocol, load and store instructions that target the mirrored memory portion of a sharer node are trapped, and store instructions that target the shared memory portion of a home node are trapped. With this protocol, valid data is obtained from the home node and updates are propagated to the home node. Thus, no 'dirty' data is transferred between sharer nodes. As a result, the failure of one node will not cause the failure of another node or the failure of the entire system.

Memory sharing across distributed nodes

Nodes in a distributed node system are configured to support memory corruption detection when memory is shared between the nodes. Nodes in the distributed node system share data in units of memory referred to herein as 'shared cache lines.' A node associates a version value with data in a shared cache line. The version value and data may be stored in a shared cache line in the node's main memory. When the node performs a memory operation, it can use the version value to determine whether memory corruption has occurred. For example, a pointer may be associated with a version value. When the pointer is used to access memory, the version value of the pointer may indicate the expected version value at the memory location. If the version values do not match, then memory corruption has occurred.

Memory corruption detection support for distributed shared memory applications

Techniques for executing versioned memory access instructions. In one embodiment, a processor is configured to execute versioned store instructions of a first thread within a first mode of operation. In this embodiment, in the first mode of operation, the processor is configured to retire a versioned store instruction only after a version comparison has been performed for the versioned store instruction. In this embodiment the processor is configured to suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction until the oldest versioned store instruction has retired. In some embodiments, the processor is configured to execute versioned store instructions of a given thread within a second mode of operation, in which the processor is configured to retire outstanding versioned store instructions before a version comparison has been performed.

Precise excecution of versioned store instructions

A system and method for transferring data and messages between nodes in a cluster is disclosed. Each node in the cluster is a separate physical domain but is connected to other nodes in the cluster through point-to-point high speed links. Each side of a link is coupled to a coprocessor which facilitates the movement of data between and among the nodes. Because each physical domain is separate from any other domain, the coprocessor in a physical domain uses a certificate, called and RKey, to obtain permission to transfer data to another physical domain. When an RKey is received from another physical domain, the coprocessor in the receiving domain validates the key and obtains the physical addresses associated with the key so that it can provide or accept the remote data. Data transfers between pairs of remote nodes in the cluster are permitted as well.

Memory bus protocol to enable clustering between nodes of distinct physical domain address spaces

Systems and methods for utilizing memory version instructions and techniques in conjunction with garbage collection in a processor. A hardware-assisted garbage collection algorithm may be executed by a computing system to move live objects between memory regions. Special store instructions may be utilized to mark the live objects of each memory region that is about to be migrated. Mutators performing useful work may be configured to trap on a memory region which is marked for migration.

Hardware assisted object memory migration

Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.

Block memory engine with memory corruption detection

Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality of threads comprising a first speculative load request, setting an indicator bit corresponding to a cache line in response to the first speculative load request, and in the event that a second speculative load request from the plurality of threads refers to a first cache line with the indicator bit set, determining if a second cache line is available.

Methods and apparatuses for improving speculation success in processors

A method and processor supporting architected instructions for tracking and determining set membership, such as by implementing Bloom filters are disclosed. The apparatus includes storage arrays (e.g., registers) and an execution core configured to store an indication that a given value is a member of a set, including by executing an architected instruction having an operand specifying the given value, wherein executing comprises applying a hash function to the value to determine an index into one of the storage arrays and setting a bit of the storage array corresponding to the index. An architected query instruction is later executed to determine if a query value is not a member of the set, including by applying the hash function to the query value to determine an index into the storage array and determining whether a bit at the index of the storage array is set.

Software-accessible hardware support for determining set membership

Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.

Efficient storage of memory version data

Systems and methods for providing additional instructions for supporting efficient memory corruption detection in a processor. A physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Version numbers associated with data structures allocated in the memory may be generated so that version numbers of adjacent data structures are different. A processor determines that a fetched instruction is a memory access instruction corresponding to a first data structure within the memory. For instructions that are not a version update instruction, the processor compares the first version number and second version number stored in a location in the memory indicated by the generated address and flags an error if there is a mismatch. For version update instructions, the processor performs a memory access operation on the second version number with no comparison check.

Instructions to set and read memory version information

The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.

Method and apparatus for using unused bits in a memory pointer

Systems and methods for maximizing a number of available states for a version number used for memory corruption detection. A physical memory may be a DRAM comprising a plurality of regions. Version numbers associated with data structures allocated in the physical memory may be generated so that version numbers of adjacent data structures in a virtual address space are different. A reserved set and an available set of version numbers are associated with each one of the plurality of regions. A version number in a reserved set of a given region may be in an available set of another region. The processor detects no memory corruption error in response to at least determining a version number stored in a memory location in a first region identified by a memory access operation is also in a reserved set associated with the first region.

Maximizing encodings of version control bits for memory corruption detection

A method for controlling a software lock acquirable by processors in a plurality of nodes of a multiprocessing system is disclosed. The method comprises a first processor of a first node of the plurality of nodes acquiring the lock, and the first processor selectively releasing the lock in a first state that allows other processors within the first node to acquire the lock but that prevents processors in a remote node of the plurality of nodes from obtaining the lock. In another embodiment, a method comprises a first processor of a first node attempting to acquire the lock, the first processor determining whether another processor within the same node is remotely spinning on the lock, and the first processor remotely spinning on the lock in response to determining that another processor in the same node is not remotely spinning on the software lock.

Multiprocessing systems employing hierarchical spin locks

In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

Value-based memory coherence support

A system and method for reducing shared memory write overhead in multiprocessor system. In one embodiment, a multiprocessing system implements a method comprising storing an indication of obtained store permission corresponding to a particular address in a store buffer. The indication may be, for example, the address of a cache line for which a write permission has been obtained. Obtaining the write permission may include locking and modifying an MTAG or other coherence state entry. The method further comprises determining whether the indication of obtained store permission corresponds to an address of a write operation to be performed. In response to the indication corresponding to the address of the write operation to be performed, the write operation is performed without invoking corresponding global coherence operations.

Growing community of inventors

San Jose, CA, United States of America

Zoran Radovic