Advanced Micro Devices Corporation

Globalfoundries Inc.

Spansion Llc.

Other

Cypress Semiconductor Corporation

Innovative Foundry Technologies B.v.

Zoran Krivokapic

Bin Yu

Haihong Wang

Judy Xilin An

Ming-Ren Lin

Matthew S Buynoski

Srikanteswara Dakshina-Murthy

An Chen

Witold P Maszara

Ognjen Milic

Qi Xiang

Mark T Ramsbey

Srinath Krishnan

Nicholas H Tripsas

William Dow Heavlin

Sunny Cherian

Bichoy Bahr

Minh Van Ngo

Arvind Halliyal

Cyrus E Tabery

Olov B Karlsson

Jusuke Ogura

Mark W Randolph

Suzette Keefe Pangrle

Shekhar Pramanick

Wei Zheng

Shibly S Ahmed

Allison Holbrook

Connie Pin-Chin Wang

Jack F Thomas

David S Bang

Geoffrey Choh-Fei Yeap

Steven J Bentley

Lu You

Jeffrey Allan Shields

Christopher A Spence

Puneet Harischandra Suvarna

Stephen G Beebe

Gen Pei

Rohit Galatage

David F Kyser

Niraj Subba

Witek Maszara

Bhanwar Singh

Paul Raymond Besser

William George En

Chih-Yuh Yang

Darrell M Erb

Dong-Hyuk Ju

Deepak K Nayak

Kai Yang

Srinivasa Banna

Jin Haeng Cho

Concetta E Riccobene

Jinsong Yin

Robert J Chiu

Ognjen Milic-Strkalj

Richard P Rouse

Bhagawan Sahu

Ahmad Ghaemmaghami

Jeffery A Shields

Brian Swanson

Nicholas H Tripisas

A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.

Negative capacitance matching in gate electrode structures

A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.

Circuit structures including a FinFET resonant body transistor are disclosed. One circuit structure includes: a plurality of fins over a substrate and a plurality of gate structures over the plurality of fins, the plurality of gate structures including at least one voltage sensing gate and multiple driving junction gates disposed on opposing sides of the at least one voltage sensing gate; at least one phononic crystal, wherein the at least one phononic crystal is arranged to confine vibrational energy arising from electrically induced mechanical stresses in the fins disposed below the driving junction gates; and, wherein the electrically induced mechanical stresses modulate carrier mobility in the at least one voltage sensing gate to produce a current extractable by the circuit structure.

Fin-FET resonant body transistor

Methods to utilize piezoelectric materials as a gate dielectric in RBTs in an IC device to generate and sense higher frequency signals with high Qs and resulting devices are disclosed. Embodiments include forming, on an upper surface of a semiconductor layer, RBTs comprising even multiples of sensing RBTs and driving RBTs, each RBT including a piezoelectric gate dielectric layer, a gate, and a dielectric spacer on opposite sides of the piezoelectric gate dielectric layer and gate, wherein at least one pair of sensing RBTs is directly between two groups of driving RBTs; forming metal layers, separated by interlayer dielectric layers, above the RBTs; and forming vias through a dielectric layer above the RBTs connecting the RBTs to a metal layer.

Methods to utilize piezoelectric materials as gate dielectric in high frequency RBTs in an IC device

Circuit structures including a FinFET resonant body transistor are disclosed. One circuit structure includes: a plurality of fins over a substrate and a plurality of gate structures over the plurality of fins, the plurality of gate structures comprising at least one voltage sensing gate, and at least two of the plurality of fins comprising multiple pn-junctions disposed on opposing sides of the at least one voltage sensing gate, the multiple pn-junctions being fabricated to operate as driving units; at least one phononic crystal, wherein the at least one phononic crystal is arranged to confine vibrational energy arising from electrically induced mechanical stresses in the fins comprising driving units; and, wherein the electrically induced mechanical stresses modulate carrier mobility in the at least one voltage sensing gate to produce a current extractable by the circuit structure.

Methods for creating barrier layers in a III-V electron channel to reduce band-to-band leakage current and the resulting devices are disclosed. Embodiments include forming a fin channel portion comprising a III-V material, on a barrier layer; forming undoped InP semiconductor spacers at opposite ends of the fin channel portion on the barrier layer; forming S/D regions adjacent the undoped InP semiconductor spacers on the barrier layer; and forming a high-k/metal gate over the fin channel portion and undoped InP semiconductor spacers.

III-V NFETs including channel barrier layers to reduce band-to-band leakage current

A semiconductor structure includes a semiconductor substrate, fins coupled to the semiconductor substrate, FinFETs on the fins, a common gate for the FinFETs, a dielectric layer on the semiconductor substrate, the dielectric layer surrounding a cavity with the semiconductor substrate providing bottom confinement of the acoustic cavity by total internal reflection, and an interconnect structure above the FinFETs, the interconnect structure including phononic crystal(s) to confine acoustic energy in the cavity including the cavity and metal layer(s) sandwiched between two dielectric layers. The semiconductor structure may be realized, during FEOL fabrication of a FinFET, by forming a cavity on a surface of a semiconductor substrate. Then, after fabrication of the FinFET, forming an interconnect structure for the FinFET. During formation of the interconnect structure, materials of the interconnect structure are used to form a phononic crystal to confine the cavity between the phononic crystal and the semiconductor substrate.

MEMs-based resonant FinFET

One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

FinFET device with a graphene gate electrode and methods of forming same

Methods and apparatus are provided for storing data in a non-volatile memory device. A method includes comparing bits of a write instruction with bits in a memory block to determine bits to be switched in the memory block; determining a switch type for each bit to be switched in the memory block; and evaluating the switch type for each bit to be switched in the memory block. The method further comprises when at least one switch type is a first switch type, performing a first operation on the memory block, and when all of the switch types are not the first switch type, performing a second operation on each bit to be switched in the memory block.

Methods and systems for memory devices with asymmetric switching characteristics

Apparatus and related fabrication and read methods are provided for crossbar memory elements. An exemplary crossbar memory element includes a crossbar array structure including a set of access lines, unswitched resistance elements coupled electrically in series between the set of access lines and a reference voltage node, and switched resistance elements coupled electrically in series between the first set of access lines and the reference voltage node. To read from a selected access line, the switched resistance element associated with that access line is enabled while the remaining switched resistance elements are disabled.

Crossbar array memory elements and related read methods

A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Double and triple gate MOSFET devices and methods for making same

A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Strained fully depleted silicon on insulator semiconductor device

A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner.

Method of forming finned semiconductor devices with trench isolation

A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Buried silicide local interconnect with sidewall spacers and method for making the same

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Santa Clara, CA, United States of America

Zoran Krivokapic