Lsi Corporation

Samsung Electronics Co., Ltd.

Avago Technologies General IP (singapore) Pte. Ltd.

Sandisk Technologies Inc.

Hitachi Global Storage Technologies Netherlands B.v.

Other

Seagate Technology Incorporated

The Texas A&M University System

Hgst Netherlands, B.v.

Zongwang Li

Shaohua Yang

Yang Han

Chung-Li Wang

Fan Zhang

Rekha Pitchumani

Weijun Tan

Yuan Xing Lee

Lei Chen

Shu Li

Wu Chang

Changyou Xu

Yang Seok Ki

Johnson Yen

Hao Zhong

Kiran Kumar Gunnam

Anatoli Aleksandrovich Bolotov

Mikhail I Grinchuk

Tong Zhang

Marie Mai Nguyen

Erich Franz Haratsch

Richard Leo Galbraith

Travis Roger Oenning

Dan Liu

Ivana Djurdjevic

Qi Zuo

Kaichi Zhang

George Mathew

Wei Zhang

Bruce Alexander Wilson

Changho Choi

Manuel Antonio d'Abreu

Mario Blaum

Kelly K Fitzpatrick

Lav D Ivanovic

Rajinikanth Pandurangan

Ksenija Lakovic

Ramzi Ammari

Abdel Hakim S Alhussien

Da Zhang

Mehran Elyasi

Haitao Xia

Wei Guang Wu

Krishna Teja Malladi

Yu Kou

Victor A Krachkovsky

Heekwon Park

Paul G Filseth

Ludovic Danjean

Jing Yang

Kaitlyn T Nguyen

Sancar Kunt Olcay

Byung Choi

AbdelHakim S Alhussien

Sahand Salamat

Armin Haj Aboutalebi

Linfang Wang

Narasimha Annapareddy

Keklik Bayam Alptekin

Susav Lal Shrestha

Chung-Li Yang

Systems and methods for prefetching data are disclosed. A processor in communication with a storage device identifies a first address. The processor identifies a first setting associated with the first address. The processor issues a first command to a first storage medium of the storage device based on the first setting. The first command is for performing a first type of memory read. The storage device is configured to retrieve first data associated with the first address in the first storage medium, to a second storage medium of the storage device, based on the first command.

Systems and methods for prefetching data

Provided are systems, methods, and apparatuses for systems and methods of memory efficient multi-vector information retrieval based on embeddings from a storage pipelined network. In one or more examples, the systems, devices, and methods include performing a first portion of a nearest neighbor search on a first subset of a set of media sources; performing a fetch process on the first subset that include identifying a first set of highest matching media sources from the first subset, transferring multi-vector representations of the first set of highest matching media sources from a storage drive to a memory, and performing a second ranking of the first set highest matching media sources. The systems, devices, and methods include performing, in parallel with the fetch process, a second portion of the nearest neighbor search on a second subset of the set of media sources.

Systems and methods for information retrieval

A system is disclosed. A storage device may store a data. A load module may read the data from the storage device based at least in part on an input/output (I/O) request. A scheduler may place the I/O request in a queue for delivery to the load module based at least in part on a size of the I/O request being less than a threshold.

Low latency multiple storage device system

A system is disclosed. The system may include a processor. The system may also include a first submission queue (SQ) and a second SQ. The first SQ may be associated with a first Quality of Service (QoS) level and the second SQ may be associated with a second QoS level, the first QoS level being different from the second QoS level. An application may be running on the processor and using a first namespace (NS). The processor may be configured to receive a first Non-Volatile Memory (NVM) Set create command to establish a first NVM Set associated with the first SQ. The processor may be further configured to receive a second NVM Set create command to establish a second NVM Set associated with the second SQ. The processor may be further configured to receive a first NS create command to establish a first NS associated with the first NVM Set. The processor may be further configured to receive a second NS create command to establish a second NS associated with the second NVM Set. The processor may be further configured to place an input/output (I/O) request sent from the application to at least one storage device in the first SQ based at least in part on the I/O request being associated with the first NS, the first NS being associated with the first NVM Set, and the first NVM Set being associated with the first SQ.

System architecture providing end-to-end performance isolation for multi-tenant systems

Systems and methods for cache management of a storage device are disclosed. The storage device is configured to receive a first code provided by a computing device; execute the first code; perform a first update of the first storage medium based on the first code; receive a second code provided by the computing device; execute the second code; and perform a second update of the first storage medium based on the second code.

Systems and methods for cache management of a storage device

A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.

Systems, methods, and apparatus for memory access in storage devices

A storage device is disclosed. The storage device may include storage for data. A controller may manage writing the data to the storage and reading the data from the storage. A data quality metric table may map a first number of errors to a first data quality metric and map a second number of errors to a second data quality metric. A transmitter may return the data quality metric table to a host.

Storage device with data quality metric and selectable data recovery scheme

Provided is a method of data storage, the method including receiving, from an application, a request to access data stored on a storage device, identifying a data access pattern of the application, and storing the data in a cache of the storage device based on the data access pattern.

Adaptive cache indexing for a storage device

A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.

Low latency SSD read architecture with multi-level error correction codes (ECC)

A method for reordering data for storage includes detecting a data access pattern, associated with an application, for accessing a data, generating a remapping function based on a data access pattern information, the remapping function including operations to determine a reordering of the data based on address information for the data, receiving the data at a storage device, the data being ordered according to a first layout sequence, reordering the data, by the storage device, based on the remapping function, and storing the data, at the storage device, according to a second layout sequence corresponding to the data access pattern, the second layout sequence being different than the first layout sequence.

Systems and methods for reordering data in a storage device based on data access patterns

An accelerator is disclosed. A circuit may process a data to produce a processed data. A first tier storage may include a first capacity and a first latency. A second tier storage may include a second capacity and a second latency. The second capacity may be larger than the first capacity, and the second latency may be slower than the first latency. A bus may be used to transfer at least one of the data or the processed data between the first tier storage and the second tier storage.

Efficient and concurrent model execution

A method for managing a memory system may include monitoring one or more accesses of a page of memory, determining, based on the monitoring, an access pattern of the page of memory, and selecting, based on the access pattern, a coherency bias for the page of memory. The monitoring may include maintaining an indication of the one or more accesses. The determining may include comparing the indication to a threshold. Maintaining the indication may include changing the indication in a first manner based on an access of the page of memory by a first apparatus. Maintaining the indication may include changing the indication in a second manner based on an access of the page of memory by a second apparatus. The first manner may counteract the second manner.

Systems, methods, and devices for bias mode management in memory systems

A storage device is disclosed. The storage device may include storage for data. A controller may manage writing the data to the storage and reading the data from the reading storage. A data quality metric table may map a first number of errors to a first data quality metric and map a second number of errors to a second data quality metric. A transmitter may return the data quality metric table to a host.

Inventive aspects include a polar code encoding system, which includes a partitioning unit to receive and partition input data into partitioned input data units. Encoders encode the partitioned input data units, and generate encoded partitioned input data units. Multiplier units perform matrix multiplication on the partitioned input data units and generator matrices, and generate matrix products. Adder units perform matrix addition on the encoded partitioned input data units and the matrix products. A combining unit combines outputs of the encoders into a target code word X. The target code word X may be a length-N code word X, where N=N+N+ . . . +N, where each of N, N, through Nare a power of two (2).

Error correction on length-compatible polar codes for memory systems

A host interface layer in a storage device is described. The host interface layer may include an arbitrator to select a first submission queue (SQ) from a set including at least the first SQ and a second SQ. The first SQ may be associated with a first Quality of Service (QoS) level, and the second SQ may be associated with a second QoS level. A command fetcher may retrieve an input/output (I/O) request from the first SQ. A command parser may place the I/O request in a first command queue from a set including at least the first command queue and a second command queue. The arbitrator may be configured to select the first SQ based at least in part on a first weight associated with the first SQ and a second weight associated with the second SQ. The first weight may be based at least in part on a first total storage capacity of at least one first namespace (NS) associated with the first QoS level, and the second weight may be based at least in part on a second total storage capacity of at least one second NS associated with the second QoS level.

Binding application to namespace (NS) to set to submission queue (SQ) and assigning performance service level agreement (SLA) and passing it to a storage device

Growing community of inventors

San Jose, CA, United States of America

Zongwang Li