Future Wei Technologies, Inc.

Western Digital (fremont), Inc.

Other

Vertical Circuits, Inc.

Huawei Technologies Co., Limited

Zongrong Liu

Lei Wang

Xiao Andy Shen

Rongsheng Miao

Hongmin Chen

Ge Yi

Qianfan Xu

Yunjun Tang

Shaoping Li

Pezhman Monadgemi

Terrence Caskey

Reynaldo Co

Scott P McGrath

Xuejin Yan

Simon J S McElrea

Scott Jay Crane

Weiping Pan

Grant Villavicencio

Lawrence Douglas Andrews, Jr

Hongzhen Wei

Huapu Pan

Yong Du

DeAnn Eileen Melcher

Yu Sheng Bai

Xueyan Zheng

Dong Li

Rongshen Miao

A piece of pick and place tool or a chip bonding equipment, which has innovative designs enabling chip(s) on a tape to get picked up without touching its front surface, is invented. The designs use levitation technologies to receive and hold the chips detached from the tape from a face-down position. A streamline design is also invented to provide better productivity. The invented pick and place tool or chip bonder is particularly useful for applications which require using chips with zero tolerance of particle and/or contamination on the chip front surfaces.

Chip front surface touchless pick and place tool or flip chip bonder

A free space coupling system comprising a waveguide horizontally positioned on an integrated circuit, and a silicon housing coupled to the waveguide, wherein the silicon housing comprises a reflective surface, a first port, wherein the first port is configured to receive light from an optic source positioned substantially parallel to the waveguide at a coupling point, and a second port, wherein the second port is oriented at about ninety degrees with respect to the first port, and wherein the second port is aligned with a grating port on the waveguide.

Free space grating coupler

A gapless optical mode converter comprising a fiber holder configured to receive and hold an optical transmission line, a first glass block coupled via an optical adhesive at a first side to the fiber holder, a lens coupled via the optical adhesive at a first side to a second side of the first glass block, and a holder configured to hold the fiber holder, the first glass block, and the lens.

Gapless optical mode converter

An edge coupling device including a substrate, a buried oxide disposed over the substrate, a cladding material disposed over the buried oxide, where the cladding material includes a trench, an inversely tapered silicon waveguide disposed within the cladding material beneath the trench, and a ridge waveguide disposed within the trench, where the ridge waveguide and the inversely tapered silicon waveguide are vertically-aligned with each other.

Edge coupling device fabrication

A method for fabricating a photonic integrated circuit (PIC) comprises providing a wafer comprising an insulator layer positioned between a top semiconductor layer and a base semiconductor layer, patterning the top semiconductor layer to simultaneously define a waveguide and a first etch mask window for forming a fiber-guiding v-groove that substantially aligns to an axis of optical signal propagation of the waveguide, removing a first portion of the top semiconductor layer to form the waveguide according to the patterning, removing a second portion of the top semiconductor layer to form the first etch mask window according to the patterning, and forming the fiber-guiding v-groove according to the first etch mask window.

Integration of V-grooves on silicon-on-insulator (SOI) platform for direct fiber coupling

A method of fabricating an edge coupling device and an edge coupling device are provided. The method includes removing a portion of cladding material to form a trench over an inversely tapered silicon waveguide, depositing a material having a refractive index greater than silicon dioxide over remaining portions of the cladding material and in the trench, and removing a portion of the material within the trench to form a ridge waveguide.

Micrometer scale components comprise a component body comprising an alloy of a first solder metal and a second solder metal, the alloy having a higher liquidus temperature than the second solder metal; and a base region of the structure body wetted to a substrate, wherein the component body has a molded surface profile.

Micrometer scale components

A monolithically integrated thermal tunable laser comprising a layered substrate comprising an upper surface and a lower surface, and a thermal tuning assembly comprising a heating element positioned on the upper surface, a waveguide layer positioned between the upper surface and the lower surface, and a thermal insulation layer positioned between the waveguide layer and the lower surface, wherein the thermal insulation layer is at least partially etched out of an Indium Phosphide (InP) sacrificial layer, and wherein the thermal insulation layer is positioned between Indium Gallium Arsenide (InGaAs) etch stop layers.

Tunable laser with high thermal wavelength tuning efficiency

A new class of the memory cell is proposed. There are two separated pulse data writing and sensing current paths. The in-plane pulse current is used to flip the magnetization direction of the perpendicular-anisotropy data storage layer sandwiched between a heavy metal writing current-carrying layer and a dielectric layer. The magnetization state within data storage layer is detected by the patterned perpendicular-anisotropy tunneling magnetoresistive (TMR) stack via the output potential of the stack. Two detailed memory cells are proposed: in one proposed cell, the data storage layer is independent from but kept close to the sensing TMR stack, whose magnetization orientation affects magnetization configuration within the free layer of the TMR stack, therefor ultimately affects the output potential of the stack; in the other proposed cell, the perpendicular-anisotropy data storage layer is the free layer of the sensing TMR stack, whose magnetization state will directly affect the output potential of the stack when sensing current passes through.

Magnetoresistive random access memory cell with independently operating read and write components

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

Magnet assisted alignment method for wafer bonding and wafer level chip scale packaging

A method for manufacturing micrometer scale components comprises depositing a first metal on a substrate, depositing a second metal in a mold, and alloying the first and second metals together to form the component.

Method of fabricating micrometer scale components

A method and system for providing a laser diode submount for use in an energy assisted magnetic recording disk drive are described. A portion of a silicon substrate is removed, forming trenches therein. Each trench has sidewalls, surrounds a silicon island corresponding to a laser diode submount, and corresponds to a thickness of the laser diode submount. The silicon island has a top surface and a facets corresponding to the trench sidewalls. Insulator(s) for the top surface and facets of the silicon island are provided. Metallization is provided on the top surface and facets of the silicon island. A first portion of the metallization on the top surface corresponds to under bump metal (UBM) for solder pad(s). A second portion of the metallization corresponds to electrical traces. Solder pad(s) are provided on the UBM. The silicon island is released from the silicon substrate.

Growing community of inventors

Pleasanton, CA, United States of America

Zongrong Liu