Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Technologies, Inc.

Via Alliance Semiconductor Co., Ltd.

Zongpu Qi

Xiaoyang Li

Zheng Wang

Lin Li

Wei Zhao

Di Hu

Jin Yu

Xuehua Han

Tao Li

Chen Chen

Fangfang Wu

Lei Meng

Dongxue Gao

Kuan-Jui Ho

Mengchen Yang

Shican Luo

Yanliang Liu

Wei Liu

Zhiqiang Hui

Xiaolu Yang

Jiamin Situ

A performance analysis system includes a picker module and a calculation circuit. The picker module is placed in the processing device to capture a plurality of pieces of time information of a unit circuit of each of a plurality of tasks in the processing device during total execution time of processing the plurality of tasks. The calculation circuit performs an interval analysis operation on the time information. The interval analysis operation includes: calculating an overlap period between a current task and a previous task; and counting time occupied by the unit circuit during the total execution time of processing the tasks by the processing device according to a relation between the current time interval of the current task corresponding to the unit circuit and the overlap period.

Performance analysis system for analyzing processing performance of processing device and method thereof

A processing system includes at least one core, at least one accelerator function unit (AFU), a microcontroller, and a memory access unit. The AFU and the core share a plurality of virtual addresses to access a memory. The microcontroller is coupled between the core and the AFU. The core develops and stores a task in one of the virtual addresses. The microcontroller analyzes the task and dispatches the task to the AFU. The AFU accesses the virtual address indicating where the task is stored through the memory access unit to executes the task.

Processing system for dispatching tasks and memory access method thereof

A processing system includes a cache, a host memory, a CPU and a hardware accelerator. The CPU accesses the cache and the host memory and generates at least one instruction. The hardware accelerator operates in a non-temporal access mode or a temporal access mode according to the access behavior of the instruction. The hardware accelerator accesses the host memory through an accelerator interface when the hardware accelerator operates in the non-temporal access mode, and accesses the cache through the accelerator interface when the hardware accelerator operates in the temporal access mode.

Hardware accelerators and access methods thereof

A processing system includes at least one core, a plurality of accelerator function unit (AFU) and a memory access unit. The memory access unit includes at least one pipeline resource and an arbitrator. The core develops a plurality of tasks. Each of the AFU is used to execute at least one of the tasks which corresponds to several memory access requests. The arbitrator selects one of the AFUs using a round-robin method at each clock period to transmit a corresponding memory access request of the selected AFU to the pipeline resource, so that the selected AFU executes the memory access request through the pipeline resource to read or write data related to the task.

Processing system with round-robin mechanism and its memory access method

A processing system includes a core, at least one accelerator function unit (AFU) and an accelerator interface. The core is utilized to develop at least one task. The AFU is utilized to execute the task. The accelerator interface is arranged between the core and the AFU to receive an accelerator interface instruction transmitted by the processing core and instruct the AFU to execute the task according to the accelerator interface instruction.

Processing system and heterogeneous processor acceleration method

An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead buffer, a string matching processing pipeline and a control circuit. The string to be compressed extracted from the data register is stored to the look-ahead buffer. A string to be compressed includes Q characters, and a repeat flag is stored in the look-ahead buffer for each character in the string to be compressed. P instances are issued in parallel in each issue cycle. When all the characters included in P substrings corresponding to the P instances are identical to each other, the control circuit sets the repeat flags of the start characters corresponding to the last (P&#x2212;1) instances among the P instances to a set state. An instance in which the repeat flag of any character of the P instances is not set to the set state is sent to the string matching processing pipeline for a matching operation, and an instance in which the repeat flags of all the characters are set to the set state is prevented from being sent to the string matching processing pipeline.

Accelerated compression method and accelerated compression apparatus

A method for encoding and compressing a bit stream is provided. The method includes: receiving a bit stream; determining whether a first number of bits that are consecutive and identical in the bit stream is greater than or equal to a first preset value; and when the first number is greater than or equal to the first preset value, the first number of bits are encoded as a first code in a first encoding way, wherein the first code is composed of a first prefix and a first suffix, and the first prefix represents what the consecutive bits are and the first suffix represents the first number.

Method and device for encoding and compressing bit stream

An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead memory, a string matching processing pipeline and a control circuit. According to an issue pointer, the control circuit issues sub-strings of a string to be compressed from the look-ahead memory to the string matching processing pipeline for a matching operation to obtain a matched length and a matched offset. The control circuit determines a new retiring position according to the matched length corresponding to a retire pointer. When the new retiring position exceeds an issuing position pointed by the issue pointer, the control circuit resets the string matching processing pipeline.

A chipset with a near-data processing (NDP) engine, which uses the NDP engine to perform a command transformation and thereby to generate an input and output (I/O) command to operate a peripheral device connected to the chipset. The chipset further has a traffic control module. The chipset receives a request to operate the peripheral device, and the traffic control module directs the request to the NDP engine to be transformed into the I/O command. The NDP engine may implement a file system, or achieve acceleration of a database or may be operated to cope with a remote direct memory access packet.

Chipset with near-data processing engine

An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead buffer, a string matching processing pipeline and a control circuit. A string to be compressed extracted from the data register is stored to the look-ahead buffer. P instances are issued in parallel from the look-ahead buffer. When P substrings corresponding to the P instances issued in a first issue cycle are identical, the control circuit sends a first instance and a second instance of the P instances to the string matching processing pipeline for a matching operation and does not send the remaining instances of these P instances to the string matching processing pipeline. In consecutive issue cycles after the first issue cycle, the control circuit does not send any of the P instances to the string matching processing pipeline until the P substrings corresponding to the P instances are not identical.

An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead buffer, a string matching processing pipeline and a control circuit. The string to be compressed extracted from the data register is stored to the look-ahead buffer. P instances are issued in parallel from the look-ahead buffer in each issue cycle. When P substrings corresponding to the instances are identical to each other, one of the P instances is sent to the string matching processing pipeline for a matching operation by the control circuit, and the remaining instances of the P instances are prevent from being sent to the string matching processing pipeline.

A chipset with a near-data processing (NDP) engine, which uses the NDP engine to perform a command transformation and thereby to generate an input and output (I/O) command to operate a peripheral device connected to the chipset. The chipset further has a traffic control module. A Remote Direct Memory Access (RDMA) packet comes from a remote computer system and is received by the chipset to operate the peripheral device. The traffic control module directs the RDMA packet to the NDP engine to be transformed into the I/O command. The NDP engine is provided to cope with the RDMA packet.

A balancing device, which is configured to balance a first duty cycle of a first accelerator and a second duty cycle of a second accelerator, includes a loading monitor and a loading balancer. The loading monitor is configured to monitor a first busy period of the first accelerator and a second busy period of the second accelerator. The loading balancer calculates the first duty cycle and the second duty cycle according to the first busy period and the second busy period, and moves at least one command queue of the first accelerator and the second accelerator according to the first duty cycle and the second duty cycle, such that the first duty cycle is close to the second duty cycle.

Balancing the loadings of accelerators

A storage device includes a memory unit, an access monitor, and a memory configurator. The memory unit includes a plurality of memory blocks. The access monitor is configured to monitor whether an access mode of the memory unit is a continuous-access mode or a random-access mode, to generate a monitor signal. The memory configurator configures, according to the monitor signal, any of the memory blocks to be either in a cache mode or a SRAM state to generate a configuration signal.

Storage device with dynamic configuration

The invention introduces a method for accelerating compression, performed in a compression accelerator, including: repeatedly executing a loop for determining the longest matched-length between a first string and a second string. Each iteration of the loop includes: obtaining n successive characters from the first string as a source string, wherein n is greater than 1; comparing each character of the source string with all characters of the second string, so as to generate n first-match-results corresponding to the n successive characters of the source string respectively; generating a second-match-result according to the n first-match-results; and determining whether a continuous match of the n successive characters is presented according to the second-match-result. If so, n is added to the matched length and the next iteration of the loop is continued to execute. Otherwise, a matched length is updated and output and the loop is exited.

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Beijing, China

Zongpu Qi