Mstar Semiconductor, Inc.

Zong-Han Wu

Chung-Ching Chen

Chen-Nan Lin

Yung Peng Chang

Hsin-Cheng Lai

A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.

Memory controller and associated signal generating method

The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command signals are generated and expanding a latching interval of a part of address signals, not only the memory controller is enabled to control the DDR memory modules in a functional manner to further overcome issues of conventionally small latching intervals, but also system stability and access performance are reinforced as the memory access clock speed continue to increase.

Growing community of inventors

Zhubei, Taiwan

Zong-Han Wu