Infineon Technologies Ag

Siemens Aktiengesellschaft

Zoltan Manyoki

Thomas B&ouml;hm

Heinz H&ouml;nigschmid

Georg Braun

Thomas R&ouml;hr

Stefan Lammers

Christian Sichert

Robert Esterl

Ernst Neuhold

Rainer Bartenschlager

Dominique Savignac

Helmut Kandolf

Norbert Wirth

Tobias Schlager

Eric Cordes

Ralf Schneider

A digital circuit configuration includes a memory matrix having M rows and N columns and P<M additional rows and Q<N additional columns, and an addressing device whose address connection contacts are sufficient precisely for addressing the M rows and N columns. To address the additional rows and columns as well, particularly, for test purposes, only a single control bit connection contact is provided with a changeover device responding to control bits from the control bit connection contact and from dedicated address connection contacts to associate applied address bits either with addressing of the M rows and N columns or the additional rows and columns. The numbers P and Q are chosen such that the addressing of P elements requires at least two bits fewer than the addressing of M elements, and such that the addressing of Q elements requires at least two bits fewer than the addressing of N elements.

Semiconductor memory device having row and column redundancy circuit and method of manufacturing the circuit

The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the plate line have a voltage equalization transistor provided between them which, in normal operation of the semiconductor circuit, can be switched to low impedance by a control signal in order to equalize the different voltages on the lines.

Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits

An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

Integrated memory and corresponding operating method

An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

Integrated memory with redundancy

A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially assigned to a respective one of the individual stages of the shift register, for identifying a chip having various required and non-required categories. The fuse device stores information from the categories to be read out serially through the shift register to identify the chip. A memory unit stores items of defined information. A logic circuit reads the fuse device for the required category and reads one of the items of defined information stored in the memory unit for the non-required category, on the basis of the categories of the chip to be identified. Standard testing of different chips is made possible while taking up little chip area.

Chip ID register configuration

The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.

Integrated memory having memory cells and reference cells, and operating method for such a memory

A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.

Decoder element for generating an output signal having three different potentials and an operating method for the decoder element

An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

Integrated memory having memory cells and reference cells, and corresponding operating method

The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.

Integrated memory

A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.

CMOS voltage divider

The invention relates to a semiconductor module for a burn-in test configuration. The semiconductor module has a regulator which, when it is turned on, always supplies a constant low voltage to an internal circuit of the semiconductor module. The semiconductor module also contains a component which, when the burn-in voltage has been applied for a defined time period, supplies a different characteristic than when the internal voltage is applied.

Semiconductor module for burn-in test configuration

The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.

Decoder element for producing an output signal having three different potentials

An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

Integrated semiconductor memory with redundant units for memory cells

An integrated memory includes a cell array having memory cells disposed at points of intersection of first bit lines and second bit lines with word lines in the cell array. When one of the memory cells is addressed, the memory content is not affected if respective bit lines associated with each of the memory cells are at a standby potential. Sense amplifiers for amplifying data read from the memory cells onto the bit lines are included, each associated with respective first and second bit lines and disposed on opposite sides of the cell array. Also provided are first switching elements, through which each bit line is connected to the associated sense amplifier, and second switching elements, through which each bit line is connected, on that side of its first switching element which is remote from the associated sense amplifier, to a standby potential. Column selection lines are each connected to the control connections of the first and second switching elements in at least one of the first and one of the second bit lines. Each bit line is connected to the standby potential through third switching elements. A first control line is connected to all the third switching elements in the first bit lines, and a second control line is connected to all the third switching elements in the second bit lines.

Integrated memory having sense amplifiers disposed on opposite sides of a cell array

An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.

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Kanata, Canada

Zoltan Manyoki