Intel Corporation

Other

Zohar Bogin

Suryaprasad Kareenahalli

David E Freker

Vincent E VonBokern

Tuong P Trieu

Serafin E Garcia

Narendra S Khandekar

Anoop Mukker

David D Lent

Darren L Abramson

Steve John Clohset

Jeffrey L Rabe

Ashish S Gadagkar

Chee Hak Teh

Steven John Clohset

Arthur Hunter, Jr

Brent D Chartrand

Romesh B Trivedi

Timothy M Dobbins

Satish Acharya

Mihir D Shah

David J Harriman

Nilesh V Shah

Aditya Sreenivas

Michael N Derr

Rajeev K Nalawadi

Vincent Edward Von Bokern

Raul N Gutierrez

Amit S Bodas

Srinivasan T Rajappa

Surya Kareenahalli

Sridhar Ramaswamy

Herbert Hing-Jing Hum

Rajagopal Subramanian

Balaji Vembu

David I Poisner

James P Kardach

Aditya Navale

Mikal Hunsaker

Randy B Osborne

Brian K Langendorf

Daniel Nemiroff

Ajay V Bhatt

Joseph A Bennett

Wishwesh Anil Gandhi

Douglas Raymond Moran

Puthiya K Nizar

Abhishek Singhal

Navneet Dour

Chai Huat Gan

Hemant G Rotithor

William Knolla

David J McDonnell

David Sastry

Jeff L Rabe

Adit D Tarmaster

Christine Watnik

Dave Freker

Sean G Galloway

Buderya S Acharya

Buderya “Satish” Acharya

Suryaprasad Kareenhalli

Suryaprasad Kareenahaili

Gautam Loonawat

Michael Tabet

Christopher D Kral

Brian L Bergeson

Zdzislaw A Wirkus

Michael G LaTondre

Tom A Sutera

Raul Gutierrez

Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.

Providing multiple virtual device controllers by redirecting an interrupt from a physical device controller

An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.

Methods and apparatuses for securing playback content

Apparatuses, methods, and systems for paging instructions for a virtualization engine to local storage. An apparatus includes a processor, a physical device controller, a virtualization engine, system memory, and local storage. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization engine is to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines. The local storage is separate from the physical memory to store instructions transferred from the system memory for execution by the virtualization engine.

Paging instruction for a virtualization engine to local storage

A method and apparatus for dedicating cache entries to certain streams for performance optimization are disclosed. The method according to the present techniques comprises partitioning a cache array into one or more special-purpose entries and one or more general-purpose entries, wherein special-purpose entries are only allocated for one or more streams having a particular stream ID.

Method and apparatus for dedicating cache entries to certain streams for performance optimization

Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream.

Stream under-run/over-run recovery

An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of the data arrival.

Dynamic adaptive read return of DRAM data

For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

Power saving for isochronous data streams in a computer system

Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Optimized memory addressing

A prioritized address decoder has been disclosed. One embodiment of the prioritized address decoder includes a first comparator to compare a destination device address of data with a first address range associated with a first device and a second comparator coupled to the first comparator to compare the destination device address with a second address range associated with a second device, wherein the data is sent to the second device in response to a first output of the first comparator and a second output of the second comparator.

Prioritized address decoder

The invention describes a technology for closing DRAM pages, wherein the invention allows for dynamically changing code streams by tracking the previous decisions made on page closes and adjusts dynamically during DRAM operation to compensate for bad page close decisions made.

Dynamic update adaptive idle timer

Embodiments of a memory scoreboard are presented herein. The memory scoreboard tracks memory requests for each rank and bank of memory being addressed. When there are no pending requests, the scoreboard provides an indication to an idle timer that begins a count down to close a current page of the memory. The idle timer can be configured dynamically to close memory pages and to address dynamically-changing code streams by tracking previous decisions made on page closes.

Pending request scoreboard for out-of-order memory scheduler

The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

High performance chipset prefetcher for interleaved channels

Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller streams the data across an isochronous channel having relaxed ordering rules to the buffer in the system memory and updates the value indicative of current position via a write across the isochronous channel to the system memory.

Tracking progress of data streamer

An address translation apparatus and method that can convert a limited-range memory address from a peripheral device to an expanded-range memory address on the fly. The invention can expand the limited address capability of a peripheral bus, such as a PCI bus with a 4 GB address range, to a much larger address capability, such as a 64 GB address range. This conversion can be performed on the fly by hardware, so that no appreciable delay in transfer time is created. The conversion can be performed by adding features to a conventional graphics controller interface, thus minimizing the impact on circuit complexity and system cost.

Remapping I/O device addresses into high memory using GART

Growing community of inventors

Folsom, CA, United States of America

Zohar Bogin