Kunlunxin Technology (beijing) Company Limited

Beijing Baidu Netcom Science and Technology Co., Ltd.

Ziyu Guo

The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

Method and apparatus for testing artificial intelligence chip, device and storage medium

A method and an apparatus for testing a chip, as well as a storage medium, and a chip thereof are provided. The chip includes an operation module. The method includes receiving, via a first pin of the chip, a test control signal indicating a test type of the operation module; performing a first test for the operation module using a first test vector based on the test type; or performing a second test for the operation module using a second test vector, where the first test is a test for the memory included in the operation module and the second test is a test for the functional logic in included in the operation module.

Method, apparatus and storage medium for testing chip, and chip thereof

Methods, apparatuses and electronic devices for testing a memory of a chip are provided. Specifically, the chip includes a plurality of operation modules, the operation module includes at least one operation unit, and the operation unit includes at least one memory. The method includes generating a first test vector for a first operation module of the operation modules, and testing the memory in the first operation module by using the generated first test vector independent of other operation modules of plurality of operation modules, where the other operation modules are different from the first operation module.

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Beijing, China

Ziyu Guo