Globalfoundries Inc.

Ziyan Xu

Chengwen Pei

Xusheng Kevin Wu

Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

Integrated circuit fabrication with boron etch-stop layer

An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming

A method of forming straight and narrow fins in the channel region and the resulting device are provided. Embodiments include forming Si fins separated by STI regions; recessing the STI regions to reveal the Si fins; forming a nitride layer over the STI regions and the Si fins; forming an OPL over the nitride layer between the Si fins; recessing the OPL to expose portions of the nitride layer over the Si fins; removing exposed portions of the nitride layer; removing the OPL; forming an oxide layer over exposed portions of the Si fins; forming a dummy gate over the nitride layer and the oxide layer perpendicular to the Si fins and surrounded by an ILD; removing the dummy gate and the oxide layer forming a cavity; thinning the Si fins in the cavity; and forming a RMG in the cavity.

Fin structure in sublitho dimension for high performance CMOS application

A method includes providing a semiconductor structure having a silicon mandrel layer, a hardmask stack and a dielectric layer. A 1portion and a 2portion of the mandrel layer are doped with a 1concentration and a 2greater concentration of dopant respectively. 1and 2mandrels are patterned into the 1and 2portions of the mandrel layer respectively. The 1and 2mandrels are oxidized in the same thermal oxidation process to form 1oxidation spacers on sidewalls of the 1mandrels and 2oxidation spacers on sidewalls of the 2mandrels. The 2oxidation spacers have a thickness that is greater than a thickness of the 1oxidation spacers. The 1and 2oxidation spacers are utilized to form 1and 2metal lines respectively in the dielectric layer. The 1and 2metal lines have a different thickness.

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Fishkill, NY, United States of America

Ziyan Xu