Qualcomm Incorporated

Zixiang Yang

Bo Sun

Gurkanwal Singh Sahota

Chiewcharn Narathong

Li Liu

Shrenik Patel

Gary John Ballantyne

Frederic Bossu

Chuan Wang

Prasad Srinivasa Siva Gudem

Steven C Ciccarelli

Dongling Pan

Wu-Hsin Chen

Wingching Vincent Leung

Yi Tang

Masoud Ensafdaran

One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.

Devices and methods for reducing noise in digitally controlled oscillators

A method for reducing power consumption on a wireless communication device is described. The wireless communication device includes a first stage active filter and a second stage active filter. A condition measurement is obtained that includes a signal measurement condition. If it is determined that the condition measurement is above a threshold, the second stage active filter is bypassed.

Reducing power consumption on a receiver

An apparatus for dividing a frequency by 1.5 to produce a quadrature signal is disclosed. The apparatus includes a divider that receives a differential input signal with a first frequency and two phases and creates a six-phase signal at a second frequency. The second frequency is the first frequency divided by 3. The apparatus also includes precision phase rotation circuitry that receives the six-phase signal and produces an eight-phase signal. The apparatus also includes a doubler that receives the eight-phase signal and produces a quadrature signal. The quadrature signal has a third frequency that is the first frequency divided by 1.5.

Dividing a frequency by 1.5 to produce a quadrature signal

A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.

Digital phase-locked loop with gated time-to-digital converter

Techniques for calibrating digitally controlled oscillators (DCOS) are disclosed. In one aspect of the disclosure, an initial set of control codes for operating the DCO with a coarse frequency tuning bank with multiple overlapping coarse frequency tuning segments (LTBs) and one fine main frequency tuning bank (MTB) is determined. A range of output frequencies produced from the initial set is identified. Instances of overlap are identified in the frequency range between consecutive LTB segments. An offset in the MTB is added that corresponds to the overlap instance between consecutive LTBs to establish a revised set. The revised control codes are utilized to tune the DCO over the desired frequency range.

Digitally controlled oscillator with improved digital frequency calibration

A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.

System and method of calibrating power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL)

A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.

High resolution time-to-digital converter

An amplifier for operating at low, middle or high linearity modes, the amplifier comprising a first low noise amplifier (LNA) coupled to a second low noise amplifier for providing amplification; a first degeneration inductor coupled to the first LNA for providing impedance matching; a &#x2212;ggeneration block coupled to an output of the second LNA for canceling third-order transconductance distortion; and a first enabling/disabling component coupled to the output of the second LNA and aligned in parallel with the &#x2212;ggeneration block for operating at least one of the first and second LNAs at one of the low, middle or high linearity modes.

Ultra low noise high linearity LNA for multi-mode transceiver

Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.

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San Diego, CA, United States of America

Zixiang Yang