Analog Devices,inc.

Ziwei Zheng

Reuben Pascal Nelson

Wyn T Palmer

Brad Porcher Jeffries

Peter Derounian

Charles D Lane

Matthew D McShea

John Jerome Kornblum

Dan Zhu

Baeton Charles Rigsbee

Oscar Sebastian Burbano

Timir Raithatha

John Cavey

Wyn Palmer

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

Frequency synthesizer with dynamic phase and pulse-width control

A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M).

Digital phase-locked loop clock system

Methods and structures are provided to improve the transfer functions of analog-to-digital converter systems. They address the converter error function that corresponds to a converter's transfer function. In particular, they provide a corrector with a corrector transfer function that defines a corrector error function which substantially mirrors at least a portion of the converter error function. The corrector processes the converter's output digital signals to realize corrector digital signals which are then combined with the original output digital signals to obtain a system with a system error function that is significantly reduced from the original converter error function.

Correction methods and structures for analog-to-digital converter transfer functions

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Greensboro, NC, United States of America

Ziwei Zheng