International Business Machines Corporation

Ziv Nevo

Shaked Flur

Alexander Ivrii

Shiri Moran

Eli Arbel

Karen Frida Yorav

Gil Eliezer Shurek

Shlomit Koyfman

Haim Kermany

Michael Shamis

Jason Raymond Baumgartner

Avi Ziv

Eyal Naor

Erez Barak

Gabor Bobok

Sima Nadler

Hana Chockler

Osher Yifrach

Sharon Keidar Barner

Tatyana Veksler

Gadiel Auerbach

Sitvanit Ruah

Shai Doron

Paul Joseph Roessler

Arie Matsliah

Raviv Gal

Roee Shlomo

Monica Farkash

Tomer Solomon

Matan Gal

Adi Sosnovich

A method, computer system, and a computer program product for determining a cluster connectivity is provided. The present invention may first include receiving as input a connectivity graph. The present invention may then include generating a minimal list of firewall rules from the received connectivity graph by iteratively merging firewall rules with commonality of connectivity attribute.

Inferring cloud network connectivity as a minimal list of firewall rules

A method, product and system including obtaining metadata associated with at least one plugin of a runtime environment, wherein the runtime environment is configured to provide a service to a client, wherein the plugin is configured to measure or enforce metrics of the service; obtaining user selections regarding the metrics, wherein the user selections comprise constraints on the runtime environment; obtaining, based on the metadata of the plugin and based on the user selections, corresponding clauses textually describing the constraints; generating a contract, wherein the contract comprises the corresponding clauses; automatically generating a configuration file based on the user selections; and automatically enforcing the contract by: activating the runtime environment, loading the service in the runtime environment, configuring the plugin according to the configuration file, executing the plugin to identify a violation of the contract, and executing a client function of the client.

Enforceable contract generation

A method, and apparatus and a computer program product for determining coverage in hardware verification based on relations between coverage events. The method comprises generating an over-approximation model of the hardware being verified to perform formal verification thereof with respect to a target coverage event being utilized in the verification process along with a set of coverage events. A score indicating an estimated conditional probability to hit the target coverage event in the verification process, given that the coverage event is hit in the verification process, may be determined for each coverage event based on the formal verification. The method further comprises selecting test suits to be executed in the verification process based on the scores and the test suits probability to hit each coverage event. The verification process may be the performed the selected test suits in order to cover the target coverage event.

Hardware verification based on relations between coverage events

A computer-implemented method, computerized apparatus and computer program product for modified design debugging using differential trace back. An indication of an interface signal in a time unit in an execution resulting in a value miscompare between a design and a modification thereof is obtained. For each of the design and the modification, a data record detailing each signal value in each time unit, and a structure description detailing all components and interconnections thereamong, are obtained. A suspect root cause of the value miscompare is traced back from the interface signal in the time unit, the tracing back comprising comparing values in the data records of candidate signals selected based on the data records and the structure descriptions.

Modified design debugging using differential trace back

A computerized method for mapping of electronic designs comprising using at least one hardware processor for receiving a first hardware design model and a second hardware design model, each hardware design model configured to receive a startup state and send digital output values. Hardware processor(s) are used for generating a plurality of initial states. Hardware processor(s) are used for computing, using each one of the first and second hardware design models, at least one specific output value for each one of the plurality of initial states. Hardware processor(s) are used for selecting corresponding initial states that produce equivalent at least one specific output value between the first hardware design model and the second hardware design model. Hardware processor(s) are used for storing the selected corresponding initial states as mappings between the first hardware design model and the second hardware design model.

Verifying sequential equivalence for randomly initialized designs

A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.

Method and apparatus for testing

Method, apparatus, and product for performing incremental formal verification. A computer-implemented method performed by a computerized device. The method comprises: obtaining invariants with respect to a first model; determining a portion of the invariants that are invariants with respect to a second model, and utilizing the portion of the invariants to check that the second model holds a property.

Incremental formal verification

Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.

Model checking of liveness property in a phase abstracted model

Augmented-domain simulation, such as ternary-based simulation may be utilized to approximate a reachability analysis of a model being model checked. The approximated reachability analysis may be utilized to detect design redundancies and modify the model to remove such redundancies. Design redundancies may include unobservable variables, mergeable variables and utilization of surplus domains.

Detection of design redundancy

Formal verification of models using concurrent model-reduction and model-checking. For example, a system for formal verification of models includes: one or more model reducers to reduce a model; one or more model checkers to check the model, wherein at least one of the model reducers is to run concurrently with at least one of the model checkers; and a model synchronizer to synchronize information between at least one of the model reducers and at least one of the model checkers.

Formal verification of models using concurrent model-reduction and model-checking

A computerized system comprising: a processor; a first interface configured to obtain a constraint; a second interface configured to obtain a first model, wherein the first model is configured to be utilized in model checking, and the first model, when constrained by the constraint, comprises at least one finite path; and a finite path removal module implemented in the processor and configured to generate a second model equivalent to the first model obtained by said second interface, wherein the second model excludes a portion of the at least one finite path, and the second model is configured to be utilized in model checking.

Model generation based on a constraint and an initial model

Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module, and presentation of the inputs on a graphical user interface. Behavior options for the design inputs are offered on the graphical user interface for selection by an operator. Environment code that is descriptive of the design inputs and selected behavior options is emitted, typically in a hardware description language, for submission to a formal verification tool. A meta-code file containing the assigned behavior options is generated to aid subsequent sessions.

System for quickly specifying formal verification environments

A method for verification of a system design represented by a model that includes a plurality of variables. The method includes arranging the variables in an Ordered Binary Decision Diagram (OBDD) according to an initial order of the variables, the OBDD including a number of nodes arranged in rows corresponding respectively to the plurality of the variables. Each processor, among a group of two or more computer processors, is assigned a respective variable among the plurality of the variables. Using each processor, the rows of the OBDD are reordered by varying a position in the OBDD of the row corresponding to the respective variable that is assigned to the processor until at least one of the processors identifies a new order for the OBDD. The new order of the OBDD may be used to verify a characteristic of the model against a specification.

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Yokneam Ilit, Israel

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