Nuvoton Technology Corporation

Winbond Electronics Corporation

Ziv Hershman

Dan Morav

Moshe Alon

Oren Tanami

Ilan Margalit

Valery Teper

Yoel Hayon

Nir Tasher

Uri Kaluzhny

Ilia Stolov

Natan Keren

Victor Adrian Flachs

Michal Schramm

Yehezkel Friedman

Yuval Kirschner

Einat Luko

Alain Bismuth

Nimrod Peled

Einat Nosovitsky

Tamir Golan

Leonid Shamis

Avraham Fishman

Boaz Tabachnik

Joram Peer

Yossi Talmi

Yael Kanter

Zeev Heller

Natan Keiren

Dana Agur

Yossef Talmi

A method includes providing one or more signals to an electronic device for performing a test procedure that involves programming a One-Time Programmable (OTP) memory in the electronic device. A verification is made as to whether connection of the one or more signals to the electronic device is stable, by performing a sequence of one or more iterations, each iteration including (i) determining, from among a set of scratchpad addresses in the OTP memory, an address that is available for programming, (ii) writing a test value to the address, and then (iii) reading the test value from the address. If the read test value differs from the written test value, re-tuning of the connection of the one or more signals is initiated. Only when the connection is verified as stable by the sequence of iterations, the OTP memory is programmed in accordance with the test procedure.

Reliable programming of one-time programmable (OTP) memory during device testing

In one embodiment, a processing device includes a symmetric block cipher configured to encrypt plaintext blocks yielding respective ciphertext blocks, obfuscation circuitry configured to obfuscate the respective ciphertext blocks responsively to an obfuscation secret yielding respective obfuscated ciphertext blocks and an interface to send the respective obfuscated ciphertext blocks to at least one remote processing device. In one embodiment, the processing device provides side-channel attack protection within a symmetric key scheme by data obfuscation and by changing encryption/decryption keys using key manipulation so that different blocks or group of blocks of data are encrypted/decrypted using respective encryption/decryption keys.

Power analysis attack protection

An electronic circuit includes a driving cell, one or more driven cells and one or more inverters. The driving cell has two or more inputs and at least one output and is configured to toggle the output between first and second logic states in response to the inputs. Each driven cell has two or more inputs, of which at least one input is configured to be driven by the output of the driving cell. The one or more inverters are placed in a signal network that connects the driving cell to the driven cells. The inverters are configured to balance, over the signal network, (i) a first capacitive load charged by electrical currents caused by transitions from the first logic state to the second logic state and (ii) a second capacitive load charged by electrical currents caused by transitions from the second logic state to the first logic state.

Protection against side-channel attacks by balancing cell drive polarity

An apparatus for protecting a processor includes an input interface and protection circuitry. The input interface is configured to monitor code instructions that are processed by the processor, one or more of which code instructions including one or more error-detection bits. The protection circuitry is configured to detect an error in the program code using the error-detection bits, and to initiate a responsive action in response to detecting the error.

Processor with in-band fault-injection detection

An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.

Integrity verification of lifecycle-state memory using multi-threshold supply voltage detection

A device including a network interface, a memory and a processor. The network interface is configured to communicate with a verifier over a communication network. The memory is configured to store multiple layers of mutable code, the layers identifiable by respective measurements. The processor is configured to generate, for a given boot cycle, a nonce associated uniquely with the given boot cycle, to receive a challenge from the verifier for attestation of a given layer of the mutable code, to calculate an attestation key based on (i) a Unique Device Secret (UDS) stored securely in the device, (ii) a measurement of the given layer taken by another layer, and (iii) the nonce generated for the given boot cycle, to calculate a response for the challenge, by signing the challenge using the attestation key, and to send the response to the verifier for verification of the given layer.

Device attestation including attestation-key modification following boot event

A method for provisioning an electronic device includes providing a semiconductor wafer on which multiple integrated circuit (IC) chips have been fabricated. Each chip includes a secure memory and programmable logic, which is configured to store at least two keys in the secure memory and to compute digital signatures over data using the at least two keys. A respective first key is provisioned into the secure memory of each of the chips via electrical probes applied to contact pads on the semiconductor wafer. After dicing of the wafer, a respective second key is provisioned into the secure memory of each of the chips via contact pins of the chips. A respective provisioning report is received from each of the chips with a digital signature computed by the logic using both of the respective first and second keys. The provisioning is verified based on the digital signature.

Multi-stage provisioning of secret data

A security device includes a bus interface and circuitry. The bus interface is coupled to a bus connecting between a host device and a peripheral device. The circuitry is configured to receive, via the bus interface, a clock signal of the bus, and to produce a delayed clock signal relative to the clock signal. The circuitry is further configured to monitor, using the clock signal, transactions communicated between the host device and the peripheral device, in response to identifying a given transaction, of which a portion is expected to be delayed by a predefined time delay relative to the clock signal, to sample the portion of the given transaction using the delayed clock signal, and in response to identifying, based on the sampled portion, that the given transaction violates a security policy, to apply a security action.

Secured communication by monitoring bus transactions using selectively delayed clock signal

A self-correcting memory system comprising an integrated circuit including memory and memory content authentication functionality, which is operative to compare content to be authenticated to a standard and to output 'authentic' if the content to be authenticated equals the standard and 'non-authentic' otherwise; and error correction functionality which is operative to apply at least one possible correction to at least one erroneous word entity in said memory, yielding a possibly correct word entity, call said authentication for application to the possibly correct word entity, and if the authentication's output is &#x201c;authentic&#x201d;, to replace said erroneous word entity in said memory, with said possibly correct word entity thereby to yield error correction at a level of confidence derived from the level of confidence associated with the authentication.

System and method for correction of memory errors

In one embodiment, a secure chip apparatus, includes a memory to store an encrypted value E and a one-way function output-value H, which is an output value of a one-way function computed with a nonce N as input, an interface to transfer data with an external device, and chip security circuitry to lock a portion of the chip apparatus from use, receive an unlock request from an unlocking hardware security module (HSM) via the interface, provide the encrypted value E to the HSM responsively to the unlock request, receive a value N' from the HSM, the value N&#x2032; being a decrypted value of the encrypted value E, compute a one-way function output-value H&#x2032; responsively to the value N&#x2032;, compare the value H&#x2032; to the value H, and unlock the portion of the chip apparatus for use responsively to a match between the value H&#x2032; and the value H.

PQA unlock

A secure Integrated Circuit (IC) includes functional circuitry, and protection circuitry configured to protect the functional circuitry against fault-injection attacks. The protection circuitry includes a plurality of digital detection cells, and protection logic. The detection cells have respective inputs and outputs and are connected output-to-input in at least a chain. In response to a fault-injection attack, a given detection cell in the chain is configured to toggle an output that drives an input of a subsequent detection cell in the chain, thereby causing a pulse to propagate along the chain. The protection logic is configured to receive the pulse from the chain and initiate a responsive action.

Digital fault injection detector

System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit.

System and method for prioritization of bit error correction attempts

An electronic device includes a combinational logic circuit, one or more functional state-sampling components, one or more protection state-sampling components, and protection logic. The combinational logic circuit has one or more outputs. The functional state-sampling components are configured to sample the respective outputs of the combinational logic circuit. The protection state-sampling components are associated respectively with the functional state-sampling components, each protection state-sampling component configured to sample a same output of the combinational logic circuit as the corresponding functional state-sampling component, but with a predefined time offset relative to the functional state-sampling component. The protection logic is configured to detect a discrepancy between the outputs sampled by the functional state-sampling components and the respective outputs sampled by the protection state-sampling components, and to initiate a responsive action in response to the discrepancy.

Data-sampling integrity check by sampling using flip-flops with relative delay

An Integrated Circuit (IC) includes functional circuitry and protection circuitry. The protection circuitry is configured to maintain a counter value, which is indicative of a cumulative amount of hostile attacking attempted on the functional circuitry over a lifetime of the IC, to detect events indicative of suspected hostile attacks on the functional circuitry, to decide, responsively to a detected event, on an update of the counter value depending on a time difference between the detected event and a most recent power-up in the IC, and update the counter value in accordance with the decided update, and to disable at least part of the IC in response to the counter value crossing a threshold.

Secure IC with soft security countermeasures

An electronic device includes clock generation circuitry, a combinational logic circuit, one or more functional state-sampling components, and protection logic. The clock generation circuitry is configured to generate a clock signal having a periodic clock cycle. The combinational logic circuit includes multiple internal nets and one or more outputs. The functional state-sampling components are configured to sample the respective outputs of the combinational logic circuit periodically in accordance with the clock signal. The protection logic is configured to receive one or more signals from the internal nets or outputs of the combinational logic circuit, to detect, in one or more of the received signals, a signal instability that occurs during a predefined portion of the periodic clock cycle in which, in accordance with a design of the combinational logic circuit, the signals are expected to be stable, and to initiate a responsive action in response to the detected signal instability.

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Giv′at-Shmuel, Israel

Ziv Hershman