Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Zion S Kwok

Ravi H Motwani

Scott Nelson

Santhosh K Vanaparthy

Poovaiah Manavattira Palangappa

Prashant S Damle

Muthukumar Swaminathan

Philip Hillier

Jeffrey W Ryden

Andre Lei

Kiran Pangal

Richard Paul Mangold

Kunal A Khochare

Aman Bhatia

Jawad Basit Khan

Pranav Kalavade

Rajesh Sundaram

Richard L Coulson

Mase J Taub

Raymond W Zeng

Bruce Querbach

Christopher Connor

Hemant P Rao

Jonathan E Schmidt

Chun Fung Kitter Man

Debarnab Mitra

Young Joon Ji

Justin Kang

Techniques and mechanisms for supporting error correction of data accessed in a non-volatile (NVM) memory. In an embodiment, a memory controller performs reads each of the same codeword from the NVM, wherein a first read is based on a first reference voltage, and a second read is based on a second reference voltage. Based on the first read and the second read, confidence values are assigned each to respective bits of the codeword. Error correction comprises applying a weights to respective bits of the codeword based on the confidence values. In other embodiments, a relatively low confidence value is assigned to codeword bits that have a different value for the first read and the second read.

Soft read for NVM that is subject to destructive reads

This application is directed to data validation and refresh in an electronic device having a memory device. The memory device receives an inquiry for a validity condition of a page of the memory device, which includes a plurality of memory cells that store two consecutive data items and correspond to two nominal threshold voltages. In response to the inquiry, the memory device selects a first readout voltage and a second readout voltage between the two nominal threshold voltages, and applies the first readout voltage and the second readout voltage to read the plurality of memory cells and generate first readout data and second readout data, respectively. An error rate of the page is determined based on the first readout data and the second readout data, and in some embodiments, further used to determine whether an error correction process or a background data refresh need to be implemented on the page.

Background data refresh using soft reads

This application is directed to data validation in an electronic device. The electronic device identifies a set of check nodes associated with a variable node that corresponds to a first data bit in a block of data, and obtains check node data from each check node. A hard decision likelihood is determined based on a check node data set including the check node data of each of the set of check nodes. The electronic device dynamically determines an adjustment factor based on the hard decision likelihood. Variable node data is determined for each of the set of check nodes based on the adjustment factor. In some embodiments, each check node is configured to verify validity of a set of data bits including the first data bit, and the check node data of each of the set of check nodes indicates a likelihood of the set of data bits being erroneous.

Variable node data management for integrity check in memory systems

A system and related method, including memory and processing circuitry, which is to receive data and corresponding expected error-detecting code value. The processing circuitry processes the data in at least two portions by calculating and storing, in memory, an error-detecting code value for the respective portion. The processing circuitry is then to calculate an overall error-detecting code value based on the respective error-detecting code values for the at least two portions. When the overall error-detecting code value does not match the expected error-detecting code value the processing circuitry is to correct at least one portion and process the corrected portions by calculating an updated error-detecting code value for a respective one of the corrected portions and calculating an updated overall error-detecting code value based on the updated error-detecting code value for each corrected portions and the stored error-detecting code values.

Methods and systems for error-detecting during iterative decoding

This application is directed to error correction for data stored in a memory device. In response to a request to validate a block of data, the memory device identifies a set of check nodes corresponding to a set of variable nodes that represent the block of data. First check node values of the check nodes are determined based on the block of data, and stored in first registers. The memory device implements a plurality of iterations of error correction by flipping a subset of variable nodes successively during each iteration; determining second check node values of the check nodes; and updating the first check node values stored in the first registers based on the second check node values once in each of a first set of iterations and successively with flipping of each variable node in a second set of iterations following the first set of iterations.

Check node updates in bit flipping decoders

Systems and methods for operating a low-density parity-check (LDPC) bit-flipping decoder are disclosed herein. An LDPC codeword is received, and each bit in the LDPC codeword is classified as either a high-confidence bit or a low-confidence bit based on at least one criterion. The LDPC codeword is iteratively processed over a plurality of iterations based on parity check equations associated with each bit of the LDPC codeword to generate a processed LDPC codeword. For each iteration of the plurality of iterations, the iterative processing includes flipping at least one bit of the LDPC codeword, while preventing, for a first n number of the plurality of iterations, bits classified as high-confidence bits from comprising more than 33% of the total number of flipped bits. The processed LDPC codeword is decoded.

Systems and methods for operating low-density parity-check bit-flipping decoder

This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.

Check node data compression in memory systems

A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

Cross-point memory read technique to mitigate drift errors

Data structure reconfiguration for low density parity checks (LDPCs) in memory systems

An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed.

Dynamic self-correction of message reliability in LDPC codes

A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.

Techniques to improve latency of retry flow in memory controllers

This application is directed to compressing a logical-to-physical (L2P) address indirection table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a set of most significant bits (MSBs) and a set of least significant bits (LSBs) of each of the plurality of physical addresses and determines a set of data bits based on a plurality of MSB sets including the set of MSBs of each of the plurality of physical addresses. The set of LSBs of each of the plurality of physical addresses and the set of data bits are stored jointly in the L2P address indirection table.

Compression of logical-to-physical address indirection table on solid-state drives

Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.

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Vancouver, Canada

Zion S Kwok