Intel Corporation

Zigi Walter

Michael Behar

Roni Rosner

Moshe Maor

Oren Agam

Ronen Gabbai

Tomer Bar-On

Jeremie Dreyfuss

Yaniv Fais

Lev Faivishevsky

Jacob Subag

Israel Diamand

Guy Jacob

Eran Ben-Avi

Neta Zmora

Orly Weisel

Shira Hirsch

Yarden Oren

Ohad Falik

Alexander Gendler

Oz Shitrit

Anat Heilper

Shlomi Shua

Henrietta Bezbroz

Shlomi Alkalay

Ravi Venkatesan

Avital Paz

Eran Nevet

Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

Methods and apparatus to configure heterogenous components in an accelerator

In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

Scheduling configuration for deep learning networks

Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload

Methods, apparatus, systems and articles of manufacture are disclosed to manage memory allocation. An example apparatus includes a memory detector to scan a platform for available memory. The example apparatus also includes a memory size checker to retrieve a virtual memory layout associated with the available memory devices associated with the platform and to determine whether virtual address boundaries of respective ones of a available memory device generate a virtual address gap therebetween. The example apparatus also includes a address assigner to reassign virtual addresses of at least one of the respective ones of the available memory devices to remove the virtual address gap.

Methods, systems, articles of manufacture and apparatus to manage memory allocation

Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.

Methods and apparatus to implement multiple inference compute engines

Methods and apparatus to dynamically throttle compute engines are disclosed. A disclosed example apparatus includes one or more compute engines to perform calculations, where the one or more compute engines are to cause a total power request to be issued based on the calculations. The example apparatus also includes a power management unit to receive the total power request and respond to the total power request. The apparatus also includes a throttle manager to adjust a throttle speed of at least one of the one or more compute engines based on comparing a minimum of the power request and a granted power to a total used power of the one or more compute engines prior to the power management unit responding to the total power request.

Methods and apparatus to dynamically throttle compute engines

Growing community of inventors

Haifa, Israel

Zigi Walter