Advanced Micro Devices Corporation

Xilinx, Inc.

Zicheng Gary Ling

Raymond T Lee

Todd P Lukanc

Jan Lodewijk De Jong

Steven P Young

Michael J Hart

Xiao-Jie Yuan

Tai-An Chao

Shihcheng Hsueh

Matthew S Buynoski

James Chiang

Yowjuang William Liu

Nagaraj Narasimh Savithri

Wei Long

Chun Jiang

Eric Richard Kent

Jayendra D Bhakta

Xin X Wu

Ming Yin Hao

Richard P Rouse

Weizhong Wang

Warren T Yu

Chiao K Hwang

Jonathan J Ho

The disclosed approaches process a circuit design that specifies a clock signal. A plurality of wire segments of an integrated circuit (IC) are selected for a clock path to carry the clock signal. A delay of the clock path is determined based on delay values associated with identifiers of the wire segments and variation factors. Configuration data is generated from the circuit design once the delay of the clock path satisfies a timing constraint, and a circuit is generated from the configuration data to implement a circuit according to the circuit design.

Determination of clock path delays and implementation of a circuit design

An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Characterizing circuit performance by separating device and interconnect impact on signal delay

A test arrangement is designed to test whether one in a chain of vias or contacts has abnormally high resistance. The arrangement contains a plurality of via or contact chains and a plurality of decoders. The chains are switchably connected to a resistance measurement device. Each decoder has a unique address such that it will generate a control signal when a predetermined address is address thereon. The control signal is used to close a switch, which connect one of the chains to the resistance measurement device. By sequentially applying different addresses to the decoders, the resistance of the chains can be individually measured.

Testing vias and contracts in integrated circuit

For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.

Method of generating an IC mask using a reduced database

A test circuit is included in an IC wafer for testing the reliability of ICS under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.

Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits

A method of testing reliability in an integrated circuit including an array of test circuits, each test circuit including a resistor. The method includes selecting a first test circuit from the array, measuring a pre-stress resistance value for the resistor in the selected test circuit, applying a high stress current across the resistor, removing the high stress current, and measuring a post-stress resistance value for the resistor. Other embodiments include measuring additional resistance values before applying and after removing the high stress current. One embodiment includes applying a positive voltage to one stress input terminal, and then testing a short sensing terminal for the positive voltage, both before and after applying the high stress current. These steps test for whether or not the high stress current has created a short in the test circuit.

Testing vias and contacts in an integrated circuit

A test circuit is included in an IC wafer for testing the reliability of ICs under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.

A method of developing a transistor, such as a complimentary MOS (CMOS) transistor, that includes lightly doped drain (LDD) regions which uses disposable spacers, and includes the step of adding an oxide spacer etch after a disposable nitride spacer removal and between source/drain implant and LDD implant. Because of this additional step, an ultra shallow LDD implant can be achieved. Moreover, uniformity of the depth of the junction is improved as the non-uniformity of the screen/liner oxide is eliminated.

Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer

Testing vias and contacts in integrated circuit fabrication

Critical dimension variation of photolithographically formed features on a semiconductor substrate is reduced by measuring the reflectivity of a photoresist layer and an underlying layer, such as a polysilicon layer, and adjusting the exposure level of the photoresist in accordance with the measured reflectivity. This allows precise control of feature width on the photoresist, which in turn allows precision etching of the underlying layer to accurately form a feature, such as a gate electrode.

Exposure correction based on reflective index for photolithographic process control

CMOS semiconductor devices comprising MOS transistors of different channel conductivity type are formed in or on a common semiconductor substrate using a minimum number of critical masks. Embodiments include forming conductive gate/insulator layer stacks on spaced-apart, different conductivity portions of the main surface of the substrate, forming etch-resistant inner sidewall spacers on side surfaces of the layer stacks, and forming easily etched, amorphous semiconductor disposable outer sidewall spacers on the inner sidewall spacers. The use of disposable outer sidewall spacers allows heavy and light source/drain implantations of opposite conductivity type to be performed for forming PMOS and NMOS transistors with the use of only two critical masks, thereby reducing production cost and duration, while increasing manufacturing throughput.

Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers

The CD variation of semiconductor devices on a wafer due to the variation in thickness of the underlying nitride layer is corrected by varying the lithographic exposure level as a function of the nitride layer thickness. Embodiments include decreasing the exposure level in areas where the nitride layer is relatively thicker.

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San Jose, CA, United States of America

Zicheng Gary Ling