Altera Corporation

Ziad M Abu-Lebdeh

Steven Perry

Christopher D Finan

Jeffrey Fox

Gregor Nixon

Alasdair Scott

Philippe Marti

Modules and methods are described for buffering packets to be switched in a system, such as a programmed device. The modules can be configured for different packet lengths, protocols, applications, and/or designs in a larger system. Techniques and mechanisms are further described for implementing a central memory and a linked-list addressing scheme. Accordingly, memory blocks of the central memory can be used for variable length packets and further reused at substantially the same time as they become available, thereby improving packet switching efficiency and/or flexibility.

Configurable central memory buffered packet switch module for use in a PLD

A method for designing a system on a programmable logic device (PLD) includes translating a timing requirement of the system into a geographical constraint. Resources on the PLD are fitted onto locations on the PLD in response to the geographical constraint.

Method and apparatus for extending the capabilities of tools used for designing systems on programmable logic devices to satisfy timing requirements

A computer-system bus switch architecture is presented that has high throughput and low latency. The architecture provides a multi-port PCI bus switch that includes a primary port controller, a crossbar switch, and a plurality of secondary port controllers. The primary port controller couples to a main system bus to which, for example, a system controller is coupled, and the secondary port controllers are each coupled to a local bus to which a plurality of peripheral devices are coupled. The crossbar switch selectively routes traffic from any port controller to any other port controller.

Growing community of inventors

Milpitas, CA, United States of America

Ziad M Abu-Lebdeh