United Microelectronics Corp.

Zi-Jun Liu

Ping-Chia Shih

Kuo-Lung Li

Chi-Cheng Huang

Hsiang-Chen Lee

Chia-Wen Wang

Chih-Hao Pan

Wen-Peng Hsu

Meng-Chun Chen

An-Hsiu Cheng

Chuan-Fu Wang

Chun-Hung Cheng

Chih-Hung Wang

Shu-Hung Yu

Chih-Yao Wang

Chia-Hui Huang

Hung-Wei Lin

Cheng-Hua Chou

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Method for fabricating semiconductor structure

Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

Semiconductor structure and method of forming the same

A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.

Semiconductor memory device and fabrication method thereof

Semiconductor structure and method for fabricating the same

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Kaohsiung, Taiwan

Zi-Jun Liu