Ford Global Technolgoies, LLC

Zhuxian Xu

Chingchi Chen

Xi Lu

Michael W Degner

Guangyin Lei

Ke Zou

Krishna Prasad Bhat

Richard William Kautz

Lan Yu

Nevin Altunyurt

Mark Allan Lippman

Jun Kikuchi

Current imbalances between parallel switching devices in a power converter half leg are reduced. A gate driver generates a nominal PWM gate drive signal for a respective half leg. A first feedback loop couples the nominal PWM gate drive signal to a gate terminal of a respective first switching device. The first feedback loop has a first mutual inductance with a current path of a first parallel switching device and has a second mutual inductance with a current path of a second parallel switching device. The first and second mutual inductances are arranged to generate opposing voltages in the first feedback loop, so that when all the parallel switching devices carry equal current then the voltages cancel.

DC inverter/converter current balancing for paralleled phase leg switches

A vehicle includes an electric machine, an IGBT, and a gate driver. The IGBT has a gate, an emitter, and a collector and is configured to flow an electric charge through a phase of the electric machine. The gate driver is configured to flow current onto the gate at a first level, and in response to a time integral of a voltage across the phase exceeding a predetermined level, transition from the first level to a second level less than the first level.

Dynamic IGBT gate drive to reduce switching loss

A multiphase inverter for an electric vehicle drive has a plurality of drivers to provide drive signals to respective gate loops of upper and lower transistors in the phase legs. A transformer has a secondary winding in a first gate loop of a first transistor in one phase leg and a primary winding connecting a Kelvin-emitter of the first transistor to a Kelvin-emitter of a second transistor in the other phase leg. Switching transients of transistors are shortened because when gate signal is toggled to change a conduction state of a transistor in a first phase leg, a rate of current change in the first leg is sensed in a transformer primary winding connected across a stray inductance of the first leg. A voltage proportional to the sensed rate is added to the gate signal via a transformer secondary winding, thereby increasing a common source inductance of the transistor.

Inverter system with enhanced common source inductance generated at gate driver

A testing apparatus includes a holster including a jack defining a conductive periphery configured to connect with a reference lead of the voltage probe to form a common ground. The apparatus includes a shunt defining first and second regions of different potential having predetermined difference. The second region is configured to connect with a reference lead of the shunt probe. The apparatus includes a bridge configured to connect the shunt probe lead with the common ground.

Power module testing apparatus

The methods and systems for correcting for an inductive load when testing high voltages devices are described. A high voltages device is a device under test (DUT) in a double-pulse test, which may require the inductive load. The method can include in a low current, high voltage time period, estimating an inductor current contribution range after a turn on of the device-under-test connected to an inductive load with an air core inductor. The method subtracts the estimated inductor current contribution from a device-under-test collector current to output a corrected collector current. This allows the double pulse test to be conducted with an air-core inductor. Vehicles can use the DUT in traction power applications.

Double-pulse test systems and methods

An inverter for an electric vehicle drive has a bridge configuration using power transistors packaged in actively cooled power modules. Control electrodes in the power modules carrying gate signals to drive the transistors contain inductive coils to increase a common source inductance in order to reduce power losses. Each inverter power module comprises a pair of transistor dies with output electrodes defining a power loop. The control electrodes with inductive coils carrying respective gate signals are arranged to be magnetically coupled with the power loop. For active cooling, a heat conductive plate underlies the dies. A magnetic interrupter is disposed at the heat conductive plate. A localized eddy current preventer is interposed at the heat conductive plate in alignment with the inductive coils to avoid eddy currents that could otherwise reduce the coupling of the inductive coils with the power loop.

Power module for inverter switching devices having gate coils shielded from eddy currents

A power module includes a packaging structure having a pair of side-by-side spaced apart busbars, each connected to a corresponding switch. The power module includes a conductive pad, between and electrically isolated from the busbars and the switches, and configured to, responsive to flow of current through the busbars generated by the switches and resulting in power loop magnetic flux between the busbars, generate magnetic flux that partially cancels the power loop magnetic flux.

Reduction of packaging parasitic inductance in power modules

A method includes measuring an impedance of a shunt as a function of frequency and converting the impedance to an admittance in a time domain. The method further includes connecting the shunt in a circuit and measuring voltage data across the shunt over a predetermined interval. The method includes outputting a signal indicative of a current through the shunt derived from the voltage data convolved with the admittance. The method may be implemented in a controller configured to interface with the shunt.

Ultra-high bandwidth current shunt

An electrified vehicle propulsion system uses current feedback to modify gate drive signals to suppress voltage spikes and increase switching efficiency. A DC link having a link capacitor and a link inductance is connected to first and second converters. A first converter bridge has a first phase leg with first upper and lower switching devices, each switching device having a respective gate loop. A second converter bridge has a second phase leg with second upper and lower switching devices, each switching device having a respective gate loop. A plurality of gate drivers provide gate drive signals to respective gate loops for turning the respective switching devices on and off. A plurality of gate coils are provided, wherein each gate coil is connected in series between a respective gate driver and a respective gate loop. Each gate coil is respectively inductively coupled to the link inductance.

DC inverter having reduced switching loss for paralleled phase leg switches

A capacitor comprising first and second end sprays respectively located at distal ends of a capacitor cell, a positive polarity bus bar extending from a first wound conductive layer of the capacitor cell adjacent to the first end spray, a negative polarity bus bar extending from a second wound conductive layer of the capacitor cell adjacent to the second end spray, and a capacitor film wrapped around an area between the first and second conductive layers.

Low inductance capacitor

A power module has upper and lower transistor dies carried by a lead frame assembly. The assembly has a positive DC paddle for the upper die and an AC paddle for the lower die. An upper plate interconnects a second side of the upper die with the AC paddle, and a lower plate interconnects a second side of the lower die with a negative power bar. Current flowing via positive and negative power bars defines a power loop creating a main magnetic flux with a first direction in a central region and a return direction outside the central region. The upper and lower plates have outer edges having respective notches to concentrate respective portions of a return magnetic flux. Each die has a gate pad connected in a gate loop, wherein the gate loops each overlap a respective concentrated return flux thereby enhancing a common source inductance for each transistor.

Inverter power module lead frame with enhanced common source inductance

A shunt includes a power terminal having a planar first potential region (FPR) connected to a second potential region (SPR) through a resistive element, the SPR being offset from and parallel to the FPR. The shunt includes a sensor terminal having a first potential lead (FPL) connected to the FPR, and a second potential lead (SPL) connected to the SPR and separated from the FPL by an insulation sheet. The SPL and sheet cover the resistive element.

Current shunt

A selectable increase in the common source inductance is obtained by a layout for a power module used for a half-bridge phase leg in an inverter for an electrically-driven vehicle. The power module comprises a pair of transistor dies connected to positive, negative, and AC conductive tracks for carrying bridge currents. The module includes a pair of gate drive pins and a pair of gate drive coils connecting a respective pin and die. The gate drive coils are disposed in a region between the positive and negative tracks containing a flux generated by the currents having a locally greatest rate of change. The coils may preferably be comprised of traces on an auxiliary printed circuit board incorporated in the module. The gate drive pins can be on the gate side or the emitter side of the transistor dies.

Inverter switching devices with gate coils to enhance common source inductance

A phase leg in an inverter bridge has an upper transistor with upper gate, collector, and emitter terminals, wherein the upper gate and emitter terminals are arranged to create an upper common source inductance. A lower transistor has lower gate, collector, and emitter terminals, wherein the lower gate and emitter terminals are arranged to create a lower common source inductance. An upper diode is coupled across the upper collector and emitter terminals and substantially in parallel with the upper common source inductance. A lower diode is coupled across the lower collector and emitter terminals and substantially in parallel with the lower common source inductance. Thus, the diodes substantially bypass the common source inductances when carrying commutation current when one of the transistors is switching off. This allows the phase leg to possess significant common source inductance at the gate terminals while avoiding 'shoot-through' issues.

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Novi, MI, United States of America

Zhuxian Xu