Globalfoundries U.S. Inc.

Globalfoundries Inc.

Zhuojie Wu

Yusheng Bian

Erdem Kaltalioglu

Karen A Nummy

Thomas F Houghton

Asli Sahin

Jennifer A Oakley

Jeremy S Alderman

Ping-Chuan Wang

Andreas Daniel Stricker

Eric D Hunt-Schroeder

Nicholas A Polomoff

Cathryn Jeanne Christiansen

Bo Peng

Ronald Gene Filippi, Jr

Dewei Xu

Seungman Choi

Yunyao Jiang

Daniel Smith

A structure includes a through semiconductor via (TSV) in a semiconductor substrate, and a dielectric liner surrounding the TSV and between the TSV and the semiconductor substrate. A plurality of discontinuous air gaps is in the semiconductor substrate extending away from the dielectric liner, e.g., radially. The discontinuous air gaps reduce the parasitic coupling capacitance and relieve stress in the semiconductor substrate.

Structure with air gaps extending from dielectric liner around through semicondcutor via

Disclosed is a photonic integrated circuit (PIC) structure including a scattering light-based monitor with photodetectors (e.g., PIN and/or avalanche photodiodes) placed adjacent to one or both sides of an end portion (i.e., a coupler) of a waveguide core at an optical interface with another optical device. The photodetectors are placed in such a way as to enable sensing of scattering light emitted from the end portion as light signals are received (e.g., either from the optical device for propagation to the main body of the waveguide core or from the main body for transmission to the optical device). Also disclosed are a monitoring system and method including the PIC chip structure with the above-described scattering light-based monitor. The system and method assess the optical interface using electric signals generated by the photodetectors.

Scattering light-based monitor for photonic integrated circuit, monitoring system and monitoring method

The disclosure relates to a PIC structure including a photonic component on a semiconductor substrate. A passive optical guard is composed of a light absorbing material and is in proximity to the photonic component. The passive optical guard includes at least a portion in an active semiconductor layer of the semiconductor substrate and may be entirely below a first metal layer. The passive optical guard may include at least one of: a germanium body positioned at least partially in a silicon element in the active semiconductor layer, a silicon body having a high dopant concentration in the active semiconductor layer, and a polysilicon body having a high dopant concentration over the silicon body.

Photonic integrated circuit including passive optical guard

Structures for a cavity-mounted chip and methods of fabricating a structure for a cavity-mounted chip. The structure comprises a substrate including a cavity, a thermoelectric device inside the cavity, and a chip disposed inside the cavity adjacent to the thermoelectric device. The thermoelectric device includes a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit, the first plurality of pillars comprising an n-type semiconductor material, and the second plurality of pillars comprising a p-type semiconductor material.

Photonics chips with thermal management for a cavity-mounted chip

A structure provides a defect sensor for a cavity in an integrated circuit (IC). The structure includes a cavity defined in a substrate. A boundary is located where the cavity meets with a cavity-free area of the substrate. A metal line is arranged in a serpentine path in both a vertical and a horizontal direction and crosses the boundary. A controller may be provided that is configured to, in response to a change in an electrical characteristic of a signal through the metal line, generate an indication of the presence of a defect and/or change operation of at least one component of the IC. The structure may find application relative to a photonics integrated circuit (PIC) structure including an optical waveguide with a cavity under the optical waveguide.

Defect detection system for cavity in integrated circuit

A photonic integrated circuit (PIC) structure includes a substrate, and a cavity defined in the substrate, the cavity including a shoulder at a side of the cavity. A plurality of z-stop supports for an optical device are also included. Each z-stop support of the plurality of z-stop supports is on a support portion of the shoulder. A wire extends over the side of the cavity and between at least two z-stop supports of the plurality of z-stop supports. An optical device is positioned on the plurality of z-stop supports in the cavity and electrically coupled to the wire. Electrical connections between z-stop supports allows larger sized electrical connections to the optical device to mitigate electromigration issues, and increased options for electrical connections.

PIC structure with wire(s) between z-stop supports on side of optical device attach cavity

An integrated circuit (IC) structure includes a substrate; and a plurality of moisture sensors along an edge of an optical input/output (I/O) opening in the substrate. The plurality of moisture sensors are positioned between a primary guard ring and a moisture barrier. The moisture sensors may detect moisture in a sequential manner to monitor moisture ingress and predict when remedial action is necessary. The teachings of the disclosure may be applicable to any IC structure including an I/O opening, and in particular, IC structures that have elongated I/O openings such as photonic integrated structures (PICs) with optical I/O openings for photonics components, e.g., an optical fiber or an external laser. The moisture sensors provide an early and definitive alarm for moisture, with no false alarms. The system accurately predicts time to failure and allows adjustment based on real time field data input.

Moisture detection along input/output opening in IC structure

An integrated circuit (IC) structure includes a moisture barrier about active circuitry. A capacitor is entirely inside the moisture barrier. The capacitor has a breakdown voltage. A moisture detector is configured to apply an increasing voltage ramp to the capacitor up to a maximum voltage less than the breakdown voltage of the capacitor. In response to determining that a current hump exists in a test current-voltage response curve of the capacitor to the increasing voltage ramp, the detector transmits a signal to the active circuitry to indicate a presence of moisture in the IC structure. The moisture detector is accurate and sensitive to moisture ingress, which provides more time for remedial action. The detector is non-destructive and can be used in a final IC product.

IC structure moisture ingress detection by current hump in current-voltage response curve

The present disclosure relates to semiconductor structures and, more particularly, to a moisture seal for photonic devices and methods of manufacture. The structure includes: a first trench in at least one substrate material; a guard ring structure with an opening and which at least partially surrounds the first trench; and a second trench at a dicing edge of the substrate, the second trench being lined on sidewalls with barrier material and spacer material over the barrier material.

Moisture seal for photonic devices

Structures for a photonics chip, testing methods for a photonics chip, and methods of forming a structure for a photonics chip. A photonics chip includes a first waveguide, a second waveguide, an optical tap coupling the first waveguide to the second waveguide, and a photodetector coupled to the second waveguide. A laser is attached to the photonics chip. The laser is configured to generate laser light directed by the first waveguide to the optical tap.

Wafer-level testing of lasers attached to photonics chips

An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

IC structure with interdigitated conductive elements between metal guard structures

A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including: a first conductive structure disposed proximate a perimeter of the IC structure; and a second conductive structure disposed parallel to the first conductive structure and proximate the perimeter of the IC structure. The sensor also includes a set of interdigitating conductive elements including a first plurality of conductive elements electrically coupled to the first conductive structure interdigitating with a second plurality of conductive elements electrically coupled to the second conductive structure.

Growing community of inventors

Port Chester, NY, United States of America

Zhuojie Wu