Cadence Design Systems, Inc.

International Business Machines Corporation

Zhuo Li

Charles Jay Alpert

Chin Ngai Sze

Natarajan Viswanathan

Mehmet Can Yildiz

Yi-Xiao Ding

Gi-Joon Nam

Yaoguang Wei

Stephen Thomas Quay

Gracieli Posser

Wen-Hao Liu

Jhih-Rong Gao

Thomas Andrew Newton

William Robert Reece

Ying Zhou

Wing-Kai Chow

Paul Gerard Villarrubia

David Anthony Papa

Derong Liu

Andrew Mark Chapman

Dirk Meyer

Shyam Ramji

Tuhin Mahmud

Kwangsoo Han

Lakshmi Narasimha Reddy

Jarrod Alexander Roy

Robert Mahlon Averill, Iii

Jose L P Neves

Amin Farshidi

Dharmendra S Modha

Myron Dale Flickner

Pallab Datta

Michael David Moffitt

Taraneh Taghavi

Ruth Patricia Jackson

Bentian Jiang

Brian Wilson

Joseph N Kozhaya

Sani Richard Nassif

Phillip John Restle

Gustavo Enrique Tellez

Jia Wang

Samuel I Ward

Haifeng Qian

Sven Peyer

Eric Jason Fluhr

Joseph J Palumbo

Andrew D Huber

Sheng-En David Lin

Matthew David Eaton

Ji Xu

Michael Alexander

George Simon Taylor

Wing Kai Chow

Su Liu

Rajiv V Joshi

Kanak Behari Agarwal

David Allan White

Shunguo Yan

Sourav Saha

Jian Li

Damir Anthony Jamsek

Rouwaida N Kanj

Myung-Chul Kim

Louise Helen Trevillyan

Joachim Gerhard Clabes

William E Dougherty, Jr

Brian C Wilson

Michael Kazda

Arjen Alexander Mets

Victor N Kravets

Christian Schulte

Karsten Muuss

Mark D Aubel

Chuck Alpert

Paul G Villarrubla

Tao Luo

Mateus Paiva Fogaça

Vitor Bandeira

James Youren

Wen Hao Liu

Yilin Zhang

Gregory F Ford

Andre Hogan

Glenn R Bee

Ben Thomas Beaumont

Shiyan Hu

Aspects of the present disclosure address systems and methods for applying logic sharing transformations to integrated circuit designs. Consistent with some embodiments, a cube-literal matrix is generated for an integrated circuit design. The cube-literal matrix comprises a non-unique matrix representation of functional logic in the integrated circuit design. A candidate cube is extracted from the cube-literal matrix to evaluate for application of a logic sharing transformation. The candidate cube comprises a sub-matrix of the cube-literal matrix corresponding to two or more common inputs of two or more logical operators. Based on determining that application of the logic sharing transformation to the candidate cube results in a reduction to a literal count in the integrated circuit design, the cube-literal matrix is updated to reflect the application of the logic sharing transformation to the candidate cube and the integrated circuit design is updated based on the updated cube-literal matrix.

Logic sharing maximization using non-unique matrix representation

Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin. An integrated circuit (IC) design stored in a database in memory is accessed. The IC design comprises a net comprising a set of driver cells. A capacitance increase margin for resizing an initial driver cell is determined based on a total capacitance of the net and transition time target associated with the initial driver cell. An alternative driver cell is selected from a library to resize the initial driver cell and is used to replace the initial driver cell in the net. The alternative driver is selected such that a pin capacitance of the alternative driver cell exceeds an initial pin capacitance corresponding to the initial driver cell by no more than the capacitance increase margin.

Driver resizing using a transition-based pin capacitance increase margin

Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.

Identifying redundant logic based on clock gate enable condition

Various embodiments provide for routing a circuit design using routing congestion based on fractional via cost, via density, or both in view of one or more design rules. For instance, some embodiments model via cost based on one or more design rules to determine routing congestion, where routing demand (e.g., routing capacity occupied by) of a via is fractional to the amount of the track blocked by the via. Additionally, some embodiments apply via density modeling based on one or more design rules to determine a routing demand of a via for routing congestion.

Routing congestion based on fractional via cost and via density

A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

Pruning redundant buffering solutions using fast timing models

Various embodiments provide for routing a net of a circuit design using rule-based routing blockage extension, which may be part of electronic design automation (EDA). In particular, some embodiments route a net of a circuit design by determining a dimension extension value based on a design rule of the circuit design and applying the dimension extension value to at least one existing routing blockage.

Routing using rule-based blockage extension

Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.

Machine-learning based clustering for clock tree synthesis

Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on leakage power and then applying cell library pruning to optimize for cell leakage power.

Grouping cells in cell library based on clustering

Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.

Post-CTS clock tree restructuring

A system includes one or more processors and a computer storage medium storing instructions that cause a machine to perform operations including accessing an integrated circuit (IC) design including an initial clock tree. The operations include selecting a first driver to evaluate for resizing, the first driver being a first size and having a first leakage current and determining a baseline power consumption measurement of clock tree based on the first size and the first leakage current of the first driver. The operations include identifying a plurality of replacement drivers to replace the first driver and determining a power consumption measurement for a second driver. Based on determining that the power consumption measurement for the second driver is less than the baseline power consumption measurement replacing the first driver with the second driver and generating a layout instance based on the second driver.

Switching power aware driver resizing by considering net activity in buffering algorithm

An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a route connecting a source to a sink. A set of buffering candidates for buffering are generated for the net. A timing improvement associated with a buffering candidate in the set of buffering candidates is determined using a first timing model. The buffering candidate is pruned from the set of buffering candidates based on the timing improvement and a cost associated with the buffering candidate. The pruned set of buffering candidates is evaluated using a second timing model, and a buffering solution for the net is selected from the pruned set of buffering candidates based on a result of the evaluating. The IC design is updated to include the buffering solution selected for the net.

Pruning of buffering candidates for improved efficiency of evaluation

An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.

Cell-width aware buffer insertion technique for narrow channels

Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Circuit design routing based on routing demand adjustment

Various embodiments provide for determining clock gates for decloning based on simulation and a satisfiability solver, which can be part of electronic design automation (EDA). In particular, some embodiments use a simulation process to quickly determine whether enable signals associated with two clock gates are logically equivalent using a random input vector to a circuit design and, if logically equivalent by the simulation process, use a satisfiability solver to determine a variable assignment (e.g., at least one vector) such that the enable signals are found to be non-equivalent.

Determining clock gates for decloning based on simulation and satisfiability solver

A system for performing operations including accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a current timing offset of the clock tree to a target timing offset. The clock tree is modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to generate an updated clock tree. During modification, the first and second locations are analyzed to determine a load reduction and increase at the respective terminals. One or more neighboring clock tree instances are adjusted to compensate for the load reduction and increase. The operations include providing an indication that the clock tree has been updated and complies with the target timing offset.

Post-CTS clock tree restructuring with ripple move

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Austin, TX, United States of America

Zhuo Li