Silicon Laboratories Inc.

Richwave Technology Corp.

Lucent Technologies Inc.

Zhuo Fu

Susumu Hara

Adam B Eldredge

Vivek Sarda

Ting-Yuan Cheng

Nicholas R Van Bavel

Pio Balmelli

Shawn R McCaslin

Hwey-Ching Chien

Mandeep Singh Chadha

Tzu-Pai Wang

Ching-Shou Huang

Tian-Tsai Chang

James E Wilson

Da-Cheng Peng

A bidirectional communication method between a master terminal and a slave terminal on a single transmission line includes the master terminal transmitting an initial message, a slave number and a master acknowledgement signal. After acknowledgement of the slave terminal, the master terminal transmits an address of the slave terminal and a master acknowledgement signal. After acknowledgement of the slave terminal, the master terminal transmits data and a master acknowledgement signal. After acknowledgement of the slave terminal, the master terminal transmits a master No-acknowledgement signal. And the slave terminal transmits a slave acknowledgement signal.

Bidirectional communication method between a master terminal and a slave terminal on a single transmission line

A digital frequency modulation receiver includes a phase capturer, an adder, a digital filter and a phase estimator. The phase estimator is used to generate a first phase value according to an input signal. The adder is coupled to the phase estimator for subtracting a second phase value from the first phase value to generate a phase difference. The digital filter is coupled to the adder for performing a filtering calculation with the phase difference so as to generate a frequency variation signal. The phase estimator is coupled to the digital filter and the adder so as to update the second phase value according to the frequency variation signal.

Digital frequency modulation receiver with frequency variation signal and demodulation method used by the same

A signal transmitter includes a modulation circuit, a signal separation circuit, and a signal combining circuit. The modulation circuit modulates a first signal to a modulated signal. The signal separation circuit separates the modulated signal into N separated signals. The N separated signals have different phases. The signal combining circuit combines the N separated signals to eliminate at least one order of harmonic signals of the N separated signals so as to generate an output signal.

Signal transmitter capable of reducing noise

One or more PLLs are formed on an integrated circuit. Each PLL includes an interpolative divider configured as a digitally controlled oscillator, which receives a reference clock signal and supplies an output signal divided according to a divide ratio. A feedback divider is coupled to the output signal of the interpolative divider and supplies a divided output signal as a feedback signal. A phase detector receives the feedback signal and a clock signal to which the PLL locks. The phase detector supplies a phase error corresponding to a difference between the clock signal and the feedback signal and the divide ratio is adjusted according to the phase error.

PLL using interpolative divider as digitally controlled oscillator

A voltage control signal at a voltage control signal input terminal is used to adjust an output frequency of an oscillator circuit. The voltage level of the voltage control signal is converted in a one-bit analog-to-digital converter (ADC) to a digital output indicative of the voltage level. Successive digital representations of the voltage level of the voltage control signal are upsampled to generate upsampled blocks of data. A dither circuit inserts a digital dither in the upsampled blocks of data to generate dithered upsampled data, which is used to generate a control signal for a feedback divider of a phase-locked loop circuit and thereby adjust the output frequency.

Voltage controlled oscillator with dither

A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.

Fractional divider

A fractional-N divider receives an input signal and supplies a divided signal divided in accordance with an integer divide control signal determined from a divide ratio. A phase interpolator is coupled to the fractional-N divider to adjust a phase of the divided signal according to a fractional portion of the divide ratio. The apparatus, responsive to a request for a frequency adjustment of the generated signal in a programmable number of steps, is configured to adjust the frequency of the generated signal from a beginning frequency to an ending frequency in the programmable number of steps by adjusting the supplied divide ratio at each step.

Frequency adjustment for clock generator

An output of an oscillator of a phase-locked loop is swept across a predetermined frequency range by varying control settings associated with the oscillator. A plurality of control settings that cause the oscillator to lock or falsely lock to the timing of an input data stream are determined at least in part according to a bit error rate. The bit error rate is based on transitions of the input data stream occurring in an error zone, the error zone being a predefined phase zone of a sample clock sampling the input data stream. When two control settings that cause the oscillator to lock or false lock are in a same locking region based on proximity of the control settings to each other, a preferred control setting is determined between the two according to respective values of the two control settings. True lock settings are distinguished from false lock settings based on an evaluation of bit errors that occur in an expanded error zone.

Robust false locking prevention in referenceless frequency acquisition

A filter circuit, method of configuring the filter circuit, and a bit pump and transceiver employing the circuit and method. In one embodiment, the filter circuit includes a noise prediction equalizer that generates a noise prediction equalizer coefficient during activation of the bit pump to reduce an intersymbol interference associated with a receive signal propagating along a receive path of the bit pump. The filter circuit also includes a decision feedback equalizer that generates a decision feedback equalizer coefficient during the activation of the bit pump to reduce the intersymbol interference associated with the receive signal. The noise prediction equalizer is concatenated with the decision feedback equalizer during showtime of the bit pump to form a precoder associated with a transmit path of the bit pump.

Growing community of inventors

Taipei, Taiwan

Zhuo Fu