Huawei Technologies Co., Limited

ZhuFeng Tan

Yu Liu

Li Zhu

Jiayin Lu

Cui Hu

Shaojie Sun

Qiang Ding

Feifei Yin

A terminal includes a security subsystem, a baseband processor, and a first bidirectional bus coupled between the security subsystem and the baseband processor. The security subsystem is configured to manage at least one of data related to a user identity or data related to network security in wireless communication, and exchange the data with the baseband processor by using the first bidirectional bus. The baseband processor is configured to exchange the data with the security subsystem by using the first bidirectional bus, and implement wireless communication by using the data. The security subsystem and the baseband processor are in the same hierarchy. The security subsystem may proactively perform data transmission by using the first bidirectional bus.

Terminal and communication method

A terminal includes a security subsystem, a baseband processor, and a first bidirectional bus coupled between the security subsystem and the baseband processor. The security subsystem is configured to manage at least one of data related to a user identity and data related to network security in wireless communication, and exchange the data with the baseband processor by using the first bidirectional bus. The baseband processor is configured to exchange the data with the security subsystem by using the first bidirectional bus, and implement wireless communication by using the data. The security subsystem and the baseband processor are in the same hierarchy. The security subsystem may proactively perform data transmission by using the first bidirectional bus.

A data protection circuit of a chip, a chip, and an electronic device, where the data protection circuit performs bit width expansion and scrambling processing on a first alarm signal using an operation circuit to obtain a second alarm signal, and outputs the second alarm signal to a processing circuit. The processing circuit performs descrambling processing after receiving the second alarm signal to obtain a descrambling result. When the second alarm signal is attacked, the descrambling fails, and the descrambling result is an active level. The processing circuit outputs the descrambling result to a reset request circuit, and the reset request circuit generates a reset request signal according to the descrambling result.

Data protection circuit of chip, chip, and electronic device

A system includes at least two buses including a first bus and a second bus, an encryption and decryption system corresponding to each bus, at least one signal processing module corresponding to each bus, and a bus converter coupled between the first bus and the second bus. According to the system provided in embodiments of the present invention, because data transmitted on a bus is encrypted data, even though an attacker obtains bus data by means of a probe attack, it is quite difficult to break a key, and an anti-attack capability of the system can be improved.

Data communication system with hierarchical bus encryption system

A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.

Chip and chip burning method

Embodiments of the present application disclose an operation method. The method includes: obtaining, by the input/output interface, an input ciphertext; performing, by the decryption circuit, a modular exponentiation operation according to the ciphertext and a preset operation parameter; and using, by the microprocessor, an operation result obtained after the modular exponentiation operation as a plaintext obtained after decryption. The performing, by the decryption circuit, a modular exponentiation operation according to the ciphertext and a preset operation parameter is specifically: breaking, by the decryption circuit, the modular exponentiation operation into multiple iterative first operations, where the first operation is a modular square operation or a modular multiplication operation; sending, by the decryption circuit, the ciphertext and the operation parameter to the arithmetic unit; and performing, by the arithmetic unit, the first operation according to the ciphertext and the operation parameter to obtain a modular square value or a modular multiplication value.

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Shanghai, China

ZhuFeng Tan