Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Zhubiao Zhu

Daniel Alan Berkram

Kenneth Koch, Ii

Dacheng Zhou

Clinton Harold Parker

John R Spencer

Ronaldo Sanchez

Hong Jiang

Cheng Li

Carson Donahue Henrion

J Robert Sims, Iii

Kehan Zhu

David J C Johnson

Michael A Buckley

Gilbert Yoh

An optical emitter includes a vertical cavity surface emitting laser (VCSEL), an equalization circuit coupled to the VCSEL; and a current source coupled to the VCSEL and the equalization circuit. The equalization circuit is configured to divert a first current from the current source to the VCSEL at a first data frequency and divert a second current greater than the first current from the current source to the VCSEL at a second data frequency higher than the first data frequency.

VCSEL equalization techniques for high speed optical transmission

An optical or an optoelectronic device and methods are provided for data transmission across two interconnects. First, an electrical signal is obtained from an interconnect. Next, the electrical signal is modulated. Within the modulated electrical signal, an occurrence of a transition is determined, in which a change in a power of the electrical signal by more than a threshold amount. In response to the determination of the occurrence of the transition, coefficients indicative of respective amounts of compensation to resolve or mitigate nonlinearities associated with the transition are determined. According to the coefficients, a filter is applied in a vicinity of the transition to obtain a modified electrical signal. The modified electrical signal is converted into an optical signal and coupled to a fiber to transmit the optical signal to a destination at a second interconnect.

Transition-based, nonlinear equalization for optical transmission

A push-pull circuit for an opto-electronic device includes: an output node; a pull-up circuit that, in operation, controls a falling edge rate of an input signal to the opto-electronic device while sharing charge with the output node; and a pull-down circuit that, in operation, controls a rising edge rate of the input signal to the opto-electronic device while sharing charge with the output node.

Push-pull circuit with driving assisted by asymmetric charge sharing

A device, including a first current supply configured to provide a bias current to a load and a main current supply having a source terminal coupled in parallel with the load and configured to reduce a current value to the load below the bias current, is provided. The device includes a termination resistor coupled in series with the source terminal of the main current supply and configured to receive current from the source terminal of the main current supply when the source terminal of the main current supply is activated. The device also includes an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, and configured to maintain the common node at common mode voltage when current flows from the source terminal of the main current supply to the sink terminal of the auxiliary current supply and through the termination resistor.

Current supply for an opto-electronic device

A device, including a switch configured to couple a current source with an output terminal upon receipt of a data signal, is provided. The device also includes a first variable capacitor coupled in parallel to the current source at a common node on a source terminal of the switch, wherein the first variable capacitor comprises multiple capacitive elements coupled in parallel and configured to be activated by a programmable signal, and wherein the programmable signal is selected to increase a charge transfer rate from an output terminal coupled to a load, when the switch is turned on. A system and a serial interface including the above device are also provided.

Driver assisted by charge sharing

An example driver circuit includes a termination voltage circuit and a termination element coupled to the termination voltage circuit. The driver circuit also includes a current source switch coupled the termination element via a node. The driver circuit further includes a current source coupled to the current source switch. The current source switch and the termination voltage circuit are controlled via a control signal. The termination voltage circuit is to generate a termination voltage to match a node voltage of the node based on the control signal. The driver circuit further includes a load coupled to the termination element and the current source switch via the node. The driver circuit further includes a load voltage source coupled to the load. The node voltage is generated based on the load and the load voltage source.

Termination voltage circuits

An example device in accordance with an aspect of the present disclosure includes at least one segment driver circuit having a first circuit and a second circuit, to receive input signals and provide output signals. A given segment driver circuit is to protect reliability and enable reconfigurability by selectively resetting coupling capacitors, and selectively cutting off the input signals from their respective segment driver circuit.

Circuits to enable reconfigurability

In one example, a device may include a first push-pull driver with a first impedance and a push-pull driver unit with a second push-pull driver having a second impedance. The push-pull driver unit may be in parallel with the first push-pull driver. The device may further include a pulse generating unit to activate the push-pull driver unit for a delay time following an edge transition in an input signal. In one example, the device may have an output impedance that is less than the first impedance when the push-pull driver unit is activated.

Devices with push-pull drivers

Apparatuses and methods for a self-biased delay looked loop with delay linearization are provided. One example delay locked loop (DLL) circuit () can include a digital-to-analog converter (DAC) () and a bias generator () communicatively coupled to an output of the DAC (). The bias generator () is configured to provide a clock signal and a bias signal. A delay control circuit (DCC) () is communicatively coupled to the bias generator (). The DCC () is configured to provide a delayed clock signal based on the clock signal and the bias signal. A DAC bias circuit () is communicatively coupled to the DAC () and configured to provide a feedback signal to the DAC () based on the bias signal. The DAC bias circuit () is configured to adjust the feedback signal to cause the delayed clock signal at the output of the DAC () to be non-linear to counteract non-linear delay characteristics of the DCC ().

Self-biased delay locked loop with delay linearization

Methods, systems, and computer-readable media are provided for operating a vertical-cavity surface-emitting laser. Operating a vertical-cavity surface-emitting laser can include sending a signal to a driver to decrease an optical power of a vertical cavity surface emitting laser transmitter, and sending a signal to the driver associated with increasing the optical power by a particular amount in response to determining that the optical power is insufficient for reception by a receiver.

Operating vertical-cavity surface-emitting lasers

Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.

Systems and methods for synchronizing an input signal

An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.

Adaptive hysteresis receiver for a high speed digital signal

A configurable metal register of an integrated circuit that allows a register output value to be changed by changing any metal or any contact within a metal pattern solution of the register. More than one metal and/or corresponding contact within the metal pattern solution may be changed so that the register output value is correspondingly changed.

Method and apparatus for a configurable metal register

An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.

Time borrowing using dynamic clock shift for bus speed performance

A system and method provide deglitch filtering. The system has a voltage-based deglitching filter and timing-based deglitching filter. The voltage-based deglitching filter connects with the timing-based deglitch filter, such that the output of the voltage-based deglitch filter connects to the input of the timing-based deglitch filter. The voltage-based deglitch filter is in feedback with the timing based deglitching filter.

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Fort Collins, CO, United States of America

Zhubiao Zhu