S3 Graphics Co., Ltd.

Via Alliance Semiconductor Co., Ltd.

Huawei Technologies Co., Limited

Future Wei Technologies, Inc.

Via Technologies, Inc.

Glenfly Tech Co., Ltd.

Zhou Hong

Konstantine I Iourcha

Krishna S Nayak

Deming Gu

Yuanfeng Wang

Yufei Zhang

Fengxia Wu

Huaisheng Zhang

Heng Que

Chih-Hong Fu

Tian Shen

Wei Zhang

Lin Chen

John W Brothers

Heng Qi

Xiaowei Yao

Chung-Kuang Chin

A method of storing data in general purpose registers (GPRs) includes packing a tile of data items into GPRs, where the tile includes multiple channels. The tile of data items is read from memory. At least two channels of the data are stored in a first GPR, and at least two additional channels are stored in a second GPR. Auxiliary data is loaded into a third GPR. The auxiliary data and the tile data can be used together for performing convolution operations.

Storing complex data in warp GPRS

The disclosed technology relates to graphics processing units (GPU), In one aspect, a GPU includes a general purpose register (GPR) including registers, an arithmetic logic unit (ALU) reading pixels of an image independently of a shared memory, and a level 1 (L1) cache storing pixels to implement a pixel mapping that maps the pixels read from the L1 cache into the registers of the GPR. The pixel mapping includes separating pixels of an image into three regions, with each region including a set of pixels. A first and second set of the pixels are loaded into registers corresponding to two of the three regions horizontally, and a third set of the pixels are loaded into registers corresponding to the third of the three regions vertically. Each of the registers in the first, second, and third registers are loaded as a contiguous ordered number of registers in the GPR.

Filter independent L1 mapping of convolution data into general purpose register

The disclosed technology generally relates to a graphics processing unit (GPU). In one aspect, a GPU includes a general purpose register (GPR) having registers, an arithmetic logic unit (ALU) configured to read pixels of an image independently of a shared memory, and a level 1 (L1) cache storing the pixels read by the ALU. The ALU can implement pixel mapping by fetching a quad of pixels, which includes pixels of first, second, third, and fourth pixel types, from the L1 cache, grouping the pixels of the different pixel types of the quad into four groups based on pixel type, and, for each group, separating the pixels included in the group into three regions that each have a set of pixels. The pixels for each group can then be loaded into the registers corresponding to the three regions.

Loading apparatus and method for convolution with stride or dilation of 2

Methodologies and architectures are provided for inter-thread sharing of data in a general purpose register (GPR) of a multiprocessor apparatus. The data sharing is performed by a graphics processing unit (GPU) having at least one processing cluster including a plurality of processing cores (PCs) configured for parallel operation. Each PC of a cluster is configured to utilize a dedicated portion of the GPR. The GPU further includes a shared memory for the cluster, and a memory read/write hub coupled to the GPR and shared memory, the hub including a crossbar switch. A PC executes a move data instruction, including operands referencing a destination portion of the GPR and a source portion assigned to the PC, to retrieve data from the source portion. The memory read/write hub writes the data, via the crossbar switch, to the destination portion of the GPR without first writing the data to the shared memory.

Inter-warp sharing of general purpose register data in GPU

A GPU comprises: a GPR comprising registers; an L1 cache coupled to the GPR and configured to implement a pixel mapping by: segregating pixels of an image into regions, the regions comprise a first region and a second region, the first region comprises first pixels, and the second region comprises second pixels, loading the first pixels into the GPR in a horizontal manner, and loading the second pixels into the GPR in a vertical manner; and an ALU configured to read the first pixels and the second pixels independently of a shared memory.

Arithmetic logic unit (ALU)-centric operations in graphics processing units (GPUs)

A dynamic voltage frequency scaling (DVFS) system is provided. The DVFS system includes: a computation unit, a power management unit (PMU), a hardware activity monitor (HAM), and a hardware voltage monitor (HVM). The HAM monitors a working status and temperature information of the computation unit, and determines whether to update an operating voltage and frequency of the computation unit according to the working status, the temperature information, and a previous determination result. When the HAM determines to update the operating voltage and frequency, the HAM generates a first control signal to the PMU to calibrate the operating voltage and frequency. The HVM detects timing information of the computation unit and determine whether to fine-tune the operating voltage according to the detected timing information. When the HVM determines to fine-tune the operating voltage, the hardware monitor generates a second control signal to the PMU to fine-tune the operating voltage.

System and method for dynamically adjusting voltage frequency

An apparatus for enqueuing kernels on a device-side is introduced to incorporate with at least a MXU (Memory Access Unit) and a CSP (Command Stream Processor): The CSP, after receiving a first command from the MXU, executes commands of a ring buffer, thereby enabling an EU (Execution Unit) to direct the MXU to allocate space of the ring buffer for a first hardware thread and subsequently write second commands of the first hardware thread into the allocated space of the ring buffer according to an instruction of a kernel.

Apparatuses for enqueuing kernels on a device-side

A graphic data compression device includes a processing unit for processing graphic data and a mixed-type compression unit for compressing the data processed by the processing unit. The mixed-type compression unit includes a lossless compression module and a nearly-lossless compression module. The lossless compression module performs a compression on processed data by a lossless compression algorithm. The nearly-lossless compression module includes an adjustment module and a compression module. The adjustment module performs an adjustment on the processed data to reduce a size of the processed data. The compression module performs, by the lossless compression algorithm, a compression on the data adjusted by the adjustment module. A graphic data compression method of the graphic data compression device is also provided. The graphic data compression device and method of the present invention reduce bandwidth load and memory occupancy, thereby effectively improving the usage of memory capacity.

Graphic data compression device and graphic data compression method

An image compression method based on JPEG-LS is presented. In the method, the M&#xd7;N pixels in the source image are divided into k groups. M, N, and k are all integers larger than one. Each group corresponds to a plurality of pixels among the M&#xd7;N pixels. The decorrelation procedure and the context modeling procedure are performed for each of the plurality of pixels in the igroup of the k groups. The compensation look-up table is not refreshed until all pixels in the igroup are performed with the decorrelation procedure and the context modeling procedure.

Image compressing method based on JPEG-LS

A graphics processing system and power gating method thereof, the graphics processing system comprising: a graphics processing unit (GPU), a bus interface and a power management unit (PMU), the GPU comprising a control circuit and a plurality of partitions; the method includes: when the bus interface receives an external graphics command, utilizing the PMU to turn on a power supply of the control circuit; subsequently utilizing the control circuit to turn on power supplies of one or more partitions of the plurality of partitions corresponding to the external graphics command; when then control circuit detects any one of the plurality of partitions is in an idle state, utilizing the control circuit to turn off the power supply of the partition in the idle state; when the bus interface detects the plurality of partitions are in a full idle state, utilizing the bus interface to turn off the power supply of the control circuit via the PMU; and when the PMU turns off the power supply of the control circuit, the control circuit may also turn off the power supplies of the plurality of the partitions.

Graphics processing system and power gating method thereof

A graphics processing unit and associated graphics processing method are provided. The graphics processing unit includes: an execution unit, for performing shader execution and texture loading; a fixed-function unit, for executing a graphics rendering pipeline; a memory-access unit; a texture unit, for reading texture data from a memory via the memory-access unit according to the data requirement of the execution unit or the fixed-function unit; and a command stream parser, for receiving a draw command from a display driver, and transmitting the draw command to the execution unit or the fixed-function unit to perform graphics processing according to the type of draw command. When the command stream parser determines that the draw command is a specific draw command, the command stream parser transmits the draw command only to the fixed-function unit to perform graphics processing, and turns off power to the execution unit.

Low-power graphics processing using fixed-function unit in graphics processing unit

A computing resource controller controlling how multiple engines share a shared resource. The controller has an arbiter, a monitoring module, an arbiter strategy control center, and an arbiter parameter updating module. The arbiter allocates access rights to the shared resource to the engines. The monitor module monitors the demands for the shared resource requested by the engines. Based on monitored results obtained from the monitoring module, the arbiter strategy control center determines an arbiter strategy suitable to the arbiter and, accordingly, the arbiter parameter updating module sets parameters of the arbiter, and the arbiter uses newly-set parameters to allocate the access rights to the shared resource to the engines.

Computing resource controller and control method for multiple engines to share a shared resource

A device for image processing includes a first queue, a second queue, a cache, and a processor. The first queue is capable of receiving a first image tile. The processor is electrically connected to the first queue, the second queue, and the cache, respectively. The processor is capable of obtaining the first image tile from the first queue and obtaining mask information of the background mask corresponding to the first tile from the cache. The processor determines the relationship between the first image tile and the background mask based on the first image tile and the mask information so as to selectively transfer the first image tile to the second queue.

Method and device for image processing

A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation. The first instructions are combined as one combined instruction according to data dependencies between the first instructions. The combined instruction is sent to a SP (Stream Processor).

Growing community of inventors

Cupertino, CA, United States of America

Zhou Hong