Boe Technology Group Co., Ltd.

Hefei Boe Joint Technology Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Beijing Shiyan Technology Co., Ltd.

Zhongyuan Wu

Yongqian Li

Liye Duan

Danna Song

Zhidong Yuan

Can Yuan

Cuili Gai

Song Meng

Kun Cao

Meng Li

Pan Xu

Dacheng Zhang

Lirong Wang

Lang Liu

Fei Yang

Jingwen Yin

Xuehuan Feng

Quanhu Li

Tieshi Wang

Dongxu Han

Gang Wang

Chi Zhang

Baoxia Zhang

Chen Song

Longyan Wang

Yuting Zhang

Jinxia Hu

Yu Wang

Yicheng Lin

Yue Wu

Mingi Chu

Szu Heng Tseng

Ming I Chu

Xue Dong

Guangcai Yuan

Wei Chen

Chen Hui Xu

Yang Zhou

Ling Wang

Yi Chen

Fang Liu

Jiankang Sun

Jiyang Shao

Jingquan Wang

Chunsheng Jiang

Wenchao Bao

Guixin Yan

Yachong Xue

Haijing Chen

Haixia Xu

Feng Liao

Yi Cheng Lin

Xingdong Liu

Szuheng Tseng

Junjie Lin

Xiangfei Zhang

Tian Xiao

Baojiang Zhang

Guang Bai

A gaze demarcating system, a method, a device, and a non-transitory computer-readable storage medium are provided. The gaze demarcating system includes: an eye movement tracking apparatus, configured to acquire pupil position coordinates; a gesture recognition apparatus, configured to acquire gesture position coordinates; a display interaction apparatus, configured to interact with a gesture; a gaze behavior determining apparatus, configured to, in a process of the display interaction apparatus interacting with the gesture, acquire a plurality of groups of effective gaze coordinates and a plurality of groups of effective gaze pupil position coordinates corresponding to the plurality of groups of effective gaze coordinates according to the gesture position coordinates and the pupil position coordinates that are acquired, the plurality of groups of effective gaze coordinates correspond to different interaction positions in a display region.

Gaze demarcating system, method, device and non-transitory computer readable storage medium

A display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a plurality of stages of shift registers including at least one first shift register and at least one second shift register, and a plurality of clock signal lines including at least one first sub-clock signal line and at least one second sub-clock signal line. Each shift register includes a first sub-circuit and a second sub-circuit. A first sub-clock signal line in the at least one first sub-clock signal line is electrically connected to a first sub-circuit in a first shift register in the at least one first shift register. A second sub-clock signal line in the at least one second sub-clock signal line is electrically connected to one sub-circuit of a first sub-circuit and a second sub-circuit in a second shift register in the at least one second shift register.

Display panel and display device

A display substrate and a display panel are provided. The display substrate includes: a base substrate; and a plurality of sub-pixels. Each sub-pixel includes a light-emitting element and a pixel circuit; the pixel circuit includes a driving circuit, a data writing circuit, a first control circuit, a second control circuit, and a light-emitting control circuit; the driving circuit is configured to control the driving current flowing through the light-emitting element; the light-emitting control circuit is configured to apply the driving current to the light-emitting element; the first control circuit is configured to write a reference voltage into the driving circuit; the second control circuit is configured to write an initial voltage into the first electrode of the light-emitting element; and orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of sub-pixels on the base substrate are mirror-symmetrical.

Display substrate having pixel circuits, and display panel

Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a base substrate, a plurality of pixel units and a plurality of gate line groups. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the positions of the sensing transistors are closer to the second gate lines, and the positions of the driving transistors are closer to the first gate line, For two sub-pixels close to each other and located in different pixel units in the same row, at least one signal line has a double-layer alignment structure, and the double-layer alignments are electrically connected with each other.

The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

Motherboard and manufacturing method for motherboard

A display substrate includes: a base substrate including a display area and a peripheral area pixel units in the display area, each including a pixel drive circuit and a light emitting device the light emitting device including a first electrode, a second electrode, and a light emitting layer; a first power trace located in the peripheral area and electrically connected to the first electrode; a second power trace located in the peripheral area and electrically connected to the second electrode; a planarization layer with at least a portion thereof being located in the peripheral area. An orthographic projection of the planarization layer on the base substrate at least partially overlaps an orthographic projection of each of the first and second power traces on the base substrate, the first and second power traces are located in different layers, and a portion of the planarization layer is located between the first and second power traces.

Display substrate and manufacturing method thereof, display panel, and display device

A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a first transistor, a second transistor and a storage capacitor. The display substrate further includes an extension portion protruding from the gate electrode of the first transistor, and the extension portion is extended from the gate electrode of the first transistor in the second direction; the extension portion is at least partially overlapped with the first electrode of the second transistor in a direction perpendicular to the base substrate and is electrically connected with the first electrode of the second transistor; in the first direction, the extension portion has a second side closest to the second capacitor electrode, and the second side is recessed in a direction away from the second capacitor electrode.

Display substrate having gate extension portion protruding from gate electrode of first transistor and display device

A pixel circuit array, a display panel, a method for driving a pixel circuit array, and a method for driving a display panel are provided. The pixel circuit array may include: a first signal sensing line (SENSE) and a second signal sensing line (SENSE); and N pixel circuits arranged in a column. All of the N pixel circuits are divided into a first group and a second group, each pixel circuit in the first group is coupled to the first signal sensing line (SENSE), and each pixel circuit in the second group is coupled to the second signal sensing line (SENSE) different from the first signal sensing line (SENSE), where N is a positive integer greater than 1.

Pixel circuit array and driving method thereof, display panel and driving method thereof

An array substrate includes: a substrate, at least one gate driving circuit and at least one clock signal line that are located on a same side of the substrate. The gate driving circuit includes a plurality of cascaded shift registers located in different rows, the plurality of shift registers are divided into at least two groups of shift registers, each group of shift registers includes at least one shift register, located in a same column. A gate driving circuit in the at least one gate driving circuit corresponds to at least one clock signal line. The clock signal line includes a main body transmission section configured to transmit a clock signal, and at least two branch transmission sections connected to the main body transmission section. Each branch transmission section is connected to a clock signal input terminal of each shift register in a respective group of shift registers.

Array substrate and manufacturing method thereof, display panel and display device

A display panel includes a substrate, a pad, an auxiliary electrode layer, a data line layer, a first electrode layer, a light emitting layer, and a second electrode layer. The substrate has a display area and a peripheral area. The pad is disposed on a side of the substrate and located in the peripheral area. The auxiliary electrode layer is disposed on the same side of the substrate as the pad; the data line layer is disposed on a same layer as the auxiliary electrode layer; the first electrode layer is disposed on a side of the auxiliary electrode layer facing away from the substrate; the light emitting layer is disposed on a side of the first electrode layer facing away from the substrate; and the second electrode layer is disposed on a side of the light emitting layer facing away from the substrate and connected to the auxiliary electrode layer.

Display device having a second electrode layer connected to an auxiliary electrode layer, display panel and manufacturing method thereof

The present application discloses a method for compensating data voltages in a display apparatus. The method for individually compensating a data voltage to be applied to one of the multiple pixel circuits in the display apparatus. The method includes obtaining a threshold voltage of the driving transistor in the one of the multiple pixel circuits. Additionally, the method includes applying a testing voltage to a gate electrode of the driving transistor for charging the sense line up to a first time period to determine a first monitoring voltage associated with the sense line. The testing voltage is set to be a sum of the threshold voltage and a first setting voltage. Moreover, the method includes compensating a data voltage to be applied to the one of the multiple pixel circuits based on the first monitoring voltage and the threshold voltage.

Data voltage compensation method, a display driving method, and a display apparatus

A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a storage capacitor. The storage capacitor includes a second capacitor electrode, a first capacitor electrode and a third capacitor electrode which are sequentially on the base substrate. The first capacitor electrode has a first capacitor electrode side and a second capacitor electrode side opposite to each other in the second direction, and the second capacitor electrode has a third capacitor electrode side and a fourth capacitor electrode side opposite to each other in the second direction; orthographic projections of the first capacitor electrode side and the second capacitor electrode side on the base substrate are between an orthographic projection of the third capacitor electrode side and an orthographic projection of the fourth capacitor electrode side on the base substrate.

Display substrate having storage capacitor with capacitor electrode sides of one capacitor electrode between capacitor electrode sides of another capacitor electrode, and display device

An image processing method, an image processing circuit and a display apparatus are provided. The image processing method includes: converting an RGB gray-scale value of each pixel in a current image frame into an RGB luminance value; converting the RGB luminance value into a first RGBW luminance value; determining a luminance level of the current image frame according to the first RGBW luminance value corresponding to each pixel; determining a luminance gain value of the current image frame according to the luminance level of the current image frame; calculating a second RGBW luminance value according to the luminance gain value and the first RGBW luminance value; and converting the second RGBW luminance value into an RGBW gray-scale value.

Image processing method, image processing circuit and display apparatus

An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, and a GOA circuit, a source electrode IC and PLG wires arranged on the base substrate, and the PLG wires connect the GOA circuit with the source electrode IC. The GOA circuit transmits a GOA signal, and the GOA signal comprises a cascade signal and a non-cascade signal. The PLG wires comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits the cascade signal, the second PLG wire group transmits the non-cascade signal, a line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located at a side of the second PLG wire group distal to an active area of the base substrate.

Array substrate and manufacturing method thereof, and display device

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Beijing, China

Zhongyuan Wu