Intel Corporation

Zhongying Zhang

Mark Dechene

Ravi Rajwar

Robert S Chappell

Sebastian Winkel

Vineeth Mekkat

Jason Bessette

Harish Kumar

Per H Hammarlund

Herbert H Hum

Douglas M Carmean

Michael D Upton

Stanley Steve Kulick

Jason M Agron

Jeffrey L Miller

Oleg Margulis

Sebastien Hily

Erik Hallnor

Manjunath Shevgoor

Jonathan Christopher Perry

Brent E Lince

John Faistl

Aravindh Baktha

Ks Venkatraman

Janghaeng Lee

Hou-Jen Ko

Faruk Guvenilir

Mike D Upton

Mark Joseph Dechene

Jason Michael Agron

An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.

Apparatus and method for an early page predictor for a memory paging subsystem

A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.

Method and apparatus for supporting speculative memory optimizations

In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.

Supporting binary translation alias detection in an out-of-order processor

A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, a cache controller of the processing device can perform one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. The cache controller can track pending line state updates to a superline outside of the tag array, and a line state update can occur in the cache controller, rather than awaiting completion of all outstanding operations on a superline. Updates to multiple line states can be maintained simultaneously, and up-to-date ECCs computed.

Method and apparatus for cache line state update in sectored cache with line state tracker

A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a cache identifying a cache line. Reading the cache line, and, if the cache line is in a Modified cache coherency protocol state, forwarding the cache line to circuitry that will cause the cache line to be written to deeper storage, and, changing another instance of the cache line that is available to the processing unit for the transactional operation to an Exclusive cache coherency state.

Method and apparatus to write modified cache data to a backing store while retaining write permissions

In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.

Hybrid cache state and filter tracking of memory operations during a transaction

Methods and apparatus for resolving false dependencies associated with speculatively executing load instructions in a processor core are described. In one embodiment, physical addresses of a load operation and a store operation are compared in response to a determination that the load operation may be potentially dependent on the store operation. Other embodiments are also described.

Resolving false dependencies of speculative load instructions

A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.

Method and apparatus for handling locks

A method of controlling operations by one or more processors includes granting ownership of a memory location having data stored therein to a first processor and performing, in an atomic manner by the first processor, a read operation to load the data from the memory location to a register, a modify operation to modify the data in the register, and a write operation to store the data from the register to the memory location. The method also prevents other operations directed towards the data by a second processor while the read, modify, and write operations are performed by the first processor, and vice versa. Ownership of the memory location is released after performing the read, modify, and write operations so as to allow the first or second processors to perform subsequent atomic operations.

Method and apparatus for lock synchronization in a microprocessor system

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Portland, OR, United States of America

Zhongying Zhang