Mstar Semiconductor, Inc.

Other

Marvellworld Trade Ltd.

Cirrus Logic Inc.

Utstarcom, Incorporated

Pixart Technology, Inc.

Zhongxuan Zhang

Bernard Ginetti

Lixin Zhao

Steve Xuefeng Jiang

Khurram Muhammad

Chih-Ming Hung

Ming-Yu Hsieh

Wei Li

Dennis Mahoney

Zhimin Zhou

Yanbin Yu

He Du

Li-Yen Shih

Yucong Gu

A system for analog computing, an analog computing system with sub-binary radix weight representation is provided. The analog computing system comprises an input node, a multiplexer (MUX), a digital to analog converter (DAC), a SRAM-based Sub-Binary Multiplier (SSBM), an analog to digital converter (ADC), a switch, an output node and a calibration module. The calibration module is configured to control the analog computing system to switch between a calibration mode and a normal operation mode. Prior to being switched to the normal operation mode, the analog computing system is configured to perform a process to calibrate a weight parameter stored in the SSBM. The ADC comprises a plurality of multipliers associated with a plurality of sub-binary weight radixes. The weight parameter stored in the SSBM and the plurality of sub-binary weight radixes are configured to represent a plurality of weights for the analog computing system.

Method and system for analog computing with sub-binary radix weight representation

A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

Multiplexed configurable sigma delta modulators for noise shaping in a 25-percent duty cycle digital transmitter

Digital input words are received in parallel by a parallel digital-to-digital sigma-delta modulator. Error words corresponding to quantization error are added in parallel to the input words to form encoded data words. The encoded data words are quantized into parallel output words and the error words resulting from such quantization are distributed across parallel modulator stages to effect a predetermined quantization error spectral distribution. The quantized output words are output in parallel.

Parallel multibit digital-to-digital sigma-delta modulation

An arbitrary modulation frequency of a modulating signal is selected. The modulating signal is applied to an information-bearing signal, where such modulation is carried out through digital signal processing operations. The digitally modulated signal is resolution-reduced and the quantization noise introduced by such is shaped to locate a spectral null in the noise transfer function of the resolution reducing modulator at the modulation frequency. Thus, the modulation frequency can be selected independently of the clock frequency at which the resolution-reduced samples are converted to an analog signal.

Digital modulation with arbitrary input sampling and output modulation frequencies

A phase detector includes a decimator to decimate a digitized in-phase signal and a digitized quadrature signal to N times a symbol rate, where N is an integer greater than one. A burst detector to detect bursts in an output of the decimator. A carrier offset block to determine an offset angle based on an output of the burst detector. A rotator to generate a rotated signal by rotating the output of the decimator based on the offset angle determined by the carrier offset block. An equalizer to perform coherent demodulation of the rotated signal.

Limiter based analog demodulator

A limiter based analog demodulator includes a power amplifier receiving a base-band signal and a local clock operating at the base-band frequency. A first multiplier receives an output from the power amplifier and the local clock to provide an in phase signal. A quadrature phase shifter receives the local clock and a second multiplier receives the output from the power amplifier and an output from the phase shifter to provide a quadrature signal. Analog filters receive the in phase and quadrature signals and analog to digital converters connected to the analog filters provide digitized in phase and quadrature signals. The phase detector then receives the digitized in phase and quadrature signals.

A digital to analog converter (DAC) for a communications system with reduced intersymbol interference incorporates dynamic element matching (DEM) with a matching element array having 2M bits for an input corresponding to M+1 levels thereby employing only one half the range of the DEM and array to produce the DAC output.

Digital to analog converter with integral intersymbol interference cancellation

An improved digital camera that produces digital images of high qualities without using expensive image sensors and optics is disclosed. The disclosed digital cameras use multiple image sensors with multiple lenses. One of the multiple image sensors is made to be responsive to all intensity information in visible color spectrum and a (gray intensity) image resulting from the sensor is used to compensate lost information in images from other image sensors responsive to certain colors. A final color image is obtained by a digital image processing circuitry that performs pixel registration process with reference to the gray intensity image so that a true color image with true resolution is obtained therefrom.

Digital cameras using multiple sensors with multiple lenses

An active pixel sensing structure includes an array of pixel unit cells each of which an adapted to alternate between a light sensing mode wherein the cell outputs an image signal and a reset mode wherein the cell outputs a reset signal. The image signal is proportional to light incident on the cell, and the reset signal is proportional to a predefined reference potential. An improved readout circuit according to the present invention includes a first sample and hold component for receiving and storing the image signal, and second sample and hold component for receiving and storing the reset signal. A signal amplifier is provided for each sample and hold component. A switching circuit is operable between a first mode and a second mode. In the second mode, the first and second sample and hold components are operatively decoupled from the corresponding signal amplifiers while input terminals of the signal amplifiers are connected to a source of predetermined reference potential. With the switching circuit in the second mode, fixed pattern noise (FPN) attributable to the amplifiers is determined. With the switching means in the first mode, a voltage, D2, is determined across outputs of the signal amplifiers. The voltage, D2, is proportional to a voltage equal to the difference between the image signal and the reset signal plus the FPN voltage. A processing means subtracts the voltage, D1, from the voltage, D2, to develop a signal proportional to the light detected by the cell.

Column readout multiplexer for CMOS image sensors with multiple readout

A VCO includes a ring oscillator formed by connecting a plurality of voltage controlled inverting delay cells together, and a plurality of transistors for providing control voltages to the plurality of voltage controlled inverting delay cells. Preferably, each transistor has a drain connected to a reference voltage, and a source connected to a voltage controlled inverting delay cell paired to that transistor. Consequently, each transistor acts as a source-follower so that it provides a control voltage to its corresponding voltage controlled inverting delay cell which follows a control voltage driving its gate, thereby isolating the control voltage provided to its corresponding voltage controlled inverting delay cell from power supply noise.

Growing community of inventors

Fremont, CA, United States of America

Zhongxuan Zhang