Changxin Memory Technologies, Inc.

Zhongming Liu

Yexiao Yu

Longyang Chen

Shijie Bai

Jia Fang

Xinman Cao

Jun Xia

Zhong Kong

Gongyi Wu

Hongfa Wu

Jiayun Zhang

Bin Zhao

Xianguo Zhou

A memory device and a method for manufacturing a memory device are provided. The memory device includes: a substrate, and a plurality of first capacitors embedded in the substrate; a plurality of first vertical transistors and a plurality of second vertical transistors, in which the plurality of first vertical transistors and the plurality of second vertical transistors are arranged on the substrate, and in which each of the plurality of first vertical transistors is electrically connected to a respective one of the plurality of first capacitors; and a plurality of second capacitors arranged on the plurality of first vertical transistors and the plurality of second vertical transistors, in which each of the plurality of second capacitors is electrically connected to a respective one of the plurality of second vertical transistors.

Memory device and method for manufacturing memory device

A semiconductor structure and the method for forming the same are provided. The method includes: providing a substrate including an active region; forming a word line in the substrate including a first portion and a second portion located at the end of the first portion, wherein the second portion of the word line protrudes from the first portion of the word line along the direction perpendicular to the substrate; forming a dielectric layer covering the substrate; and etching the dielectric layer and a part of the substrate to simultaneously form a first contact hole exposing the second portion of the word line and a second contact hole exposing the active region. The invention reduces the etching time and improves the etching efficiency. It avoids an excessively large etching depth of the second contact hole, thereby reducing the damage to the active region and the leakage current inside the semiconductor structure.

Semiconductor structure and method for forming same

The present application discloses a semiconductor structure and a method for fabrication. This technique improves the stability of the bit line structure. The semiconductor structure is formed in a bit line trench in a substrate, it includes: a bit line conductive layer formed in the bit line trench, and the top surface of the bit line conductive layer is higher the top surface of the substrate; a barrier layer formed at least partially between the bit line conductive layer and the inner wall of the bit line trench; and an isolation layer formed on top of the bit line conductive layer.

Method of forming a bit line structure

Provided is a semiconductor structure and a method for manufacturing the same. The method includes forming a spin on hard mask layer on a base, active areas arranged at intervals in the base, bit lines arranged at intervals and extending in a first direction on the base, each bit line electrically connected to at least one active area, and the spin on hard mask layer filled between the bit lines and covering the bit lines; removing part of the spin on hard mask layer to form first trenches arranged at intervals and extending in a second direction; forming first sacrificial layers in the first trenches; removing the spin on hard mask layer between the first sacrificial layers to form second trenches; forming first supporting layers in the second trenches; removing the first sacrificial layers and elongating the first trenches located between adjacent bit lines to the active areas.

Semiconductor structure and method for manufacturing same

The present disclosure provides a memory device, and a semiconductor structure and a forming method thereof, which includes: providing a substrate, which includes a plurality of bit line structures, forming a cover layer on each of the bit line structures, forming a first insulating layer and a second insulating layer sequentially on a side wall of each cover layer, and filling a space between second insulating layers of two adjacent bit line structures with a conductive contact layer; tops of the conductive contact layers and the second insulating layers are all lower than surfaces of the cover layers and higher than surfaces of the bit line structures; tops of the first insulating layers are flush with those of the conductive contact layers and the second insulating layers; and etching back the conductive contact layers, to form a capacitor contact hole between cover layers of two adjacent bit line structures.

Memory device, and semiconductor structure and forming method thereof

A method for manufacturing a semiconductor structure includes: providing a substrate, a first mask and a second mask, etching the substrate by respectively using the first mask and the second mask, so as to form first grooves and second grooves on the substrate, wherein regions, in the substrate, where the first grooves and the second grooves are located form bit line grooves; and forming a conductive layer in each of the bit line grooves.

Method for manufacturing semiconductor structure, and semiconductor structure

The present application relates to the technical field of manufacturing semiconductor, and in particular to a method of manufacturing semiconductor structure and a semiconductor structure. The method of manufacturing semiconductor structure includes: forming a conductive layer on a substrate, and removing part of the conductive layer to form a contact structure composed of a plurality of contact pads; where each of the contact pads is electrically connected to a transistor structure on the substrate; and, after the contact pads are formed, removing residual core on top ends of the contact pads away from the substrate by dry etching.

Method of manufacturing semiconductor structure and semiconductor structure

Embodiments provide a semiconductor structure and a fabricating method. The method includes: providing a substrate, where a plurality of active areas arranged at intervals are provided in the substrate, and the substrate is covered with an insulating layer and a barrier layer stacked sequentially; forming, in the barrier layer, a plurality of first trenches arranged at intervals and extending along a first direction and penetrating through the barrier layer; forming a filling layer in the first trenches, and forming a first mask layer on the barrier layer and the filling layer; forming, in the first mask layer, a plurality of second trenches arranged at intervals and extending along a second direction and exposing the filling layer; and removing the filling layer exposed in the second trench and the insulating layer corresponding to the filling layer to form contact holes.

Semiconductor structure and method for fabricating same

A preparation method for a semiconductor structure and a semiconductor structure are provided. Herein, the preparation method comprises: providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate; patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer; forming spacers with vertical sidewall morphology on sidewalls of the first mask layer; removing the first mask layer; filling a gap between the spacers with a filling layer, in which a material of the spacers to a material of the filling layer has a high etching selectivity ratio; and removing the spacers.

Preparation method for semiconductor structure and same

A manufacturing method of a semiconductor structure includes: providing a base; forming multiple bit line structures on the base, where the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures; forming a first conductive layer in the trench, where a void is formed in the first conductive layer; removing a part of the first conductive layer to form a first groove, where the bottom of the first groove exposes the void; forming an epitaxial layer on an inner wall of the first groove; and allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void.

Manufacturing method of semiconductor structure with epitaxial layer forming extension portion

A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.

Semiconductor structure and manufacturing method thereof

A method for preparing a capacitor contact structure of a memory device includes providing a substrate, forming a plurality of bit line structures arranged in parallel and at intervals on the substrate, and the bit line structures extending along a first direction; forming conducting layer structures between adjacent bit line structures, upper surfaces of which are lower than upper surfaces of the bit line structures; forming sacrificial layers on the conducting layer structures; forming a plurality of isolation trenches arranged in parallel and at intervals in the sacrificial layer, the isolation trenches extend along a second direction, and the second direction intersects the first direction; forming isolation dielectric layers in the isolation trenches; and removing the sacrificial layer based on the bit line structure and the isolation dielectric layer to form grooves between adjacent bit line structures and between adjacent isolation dielectric layers, the grooves expose the conducting layer structures.

Memory device capacitor contact structure and method for preparing same

A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method for manufacturing a semiconductor structure includes: forming a conductive layer, a protective layer, and a mask layer in sequence on the substrate, the mask layer including a first pattern facing the first region and a second pattern facing the second region; forming a restriction pattern located in the second region by etching the protective layer using the mask layer as a mask; and forming contact pads located in the first region and connecting wires located in the second region on the conductive layer by etching the conductive layer using the mask layer as a mask.

Method for manufacturing semiconductor structure and semiconductor structure

Embodiments provide a method for fabricating a memory and a memory. This method includes: providing a substrate, the substrate being internally provided with a plurality of active areas, and each of the plurality of active areas including a first contact region and a second contact region; forming a plurality of bit lines on the substrate, each of the plurality of bit lines being connected to at least one of the first contact regions; forming an isolation layer on each of the plurality of bit lines, the isolation layer covering each of the plurality of bit lines and the substrate, the isolation layer being further provided with a plurality of filling holes corresponding to the plurality of second contact regions one to one; etching the isolation layer and the substrate along the plurality of filling holes, to fill in the plurality of second contact regions.

Method for fabricating memory and memory

A method for manufacturing a semiconductor structure includes: providing a base, in which a plurality of bit lines extending in a first direction and a groove located between two adjacent ones of the bit lines are provided on the base; forming an initial contact layer and an initial protection layer filling the groove, in which the initial contact layer is in contact with the base, the initial protection layer is located on the initial contact layer; patterning the initial contact layer and the initial protection layer to form contact layers that are discrete from each other and protection layers that are discrete from each other; and forming a dielectric layer between two adjacent ones of the contact layers, in which the dielectric layer is further located between two adjacent ones of the protection layers, a material of the dielectric layer is different from a material of the protection layer.

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Hefei, China

Zhongming Liu