Ami Semiconductor, Inc.

Zhongmin Li

Bryce A Rasmussen

Troy L Ruud

Shan Mo

A differential voltage signal (LVDS) driver circuit and/or a Current Mode Logic (CML) driver circuit. The circuit includes two current switches, each coupled to a corresponding input node. In a complementary manner, when a differential signal is applied across the input nodes, one current switch is open, while the other current switch is closed, and vice versa. A current allocation component allocates current between the two input current switches such that, when the first current switch is closed and the second current switch is open, increasing current is allocated through the first current switch and the intervening current path between the current allocation component and the first current switch, and vice versa. The circuit includes complementary pre-emphasis and/or current-aided pre-emphasis mechanisms that boost differential output transmission edges.

Differential signal driver having complimentary and current-aided pre-emphasis

A differential signal output driver circuit having four switching transistors and having a bias transistor that shields each of the switching transistors from the corresponding output terminal thereby blocking the Miller capacitance of the switching capacitor from generating overshoot or undershoot in the output differential voltage. Also, the output driver circuit may be driven by a differential skew cancellation circuit that generates a balanced differential signal to drive the switching transistors to further improve signal integrity. The signal path for generating each signal in the differential signal goes through a similar structure thereby ensuring similar slew in each differential signal provided to the output driver circuit.

Low-voltage differential signal (LVDS) transmitter with high signal integrity

A digitally controlled impedance driver circuit including a number of fingers, some of which having FETs and series resistors sized in binary or other differential ratios, and some of the higher power FETs being sized in equal ratio and perhaps sharing a series resistor. A DCI controller circuit periodically determines a configuration of the DCI driver circuit that would result in the DCI driver circuit approximating a target impedance. Each time the DCI controller circuit does this, a comparator determines if the impedance of the DCI driver circuit should be increased or decreased. A noise attenuation circuit turns off (or on) only one of the high power fingers if the controller circuit determines that more (or less) impedance is needed even if turning off (or on) only one of the fingers would not result in the configuration of the DCI driver circuit determined by the controller circuit.

Digitally controlled impedance driver matching for wide voltage swings at input/output node and having programmable step size

A complementary differential amplifier includes two differential amplifiers. Each differential amplifier includes two input FETs (or bipolar transistors) having gate terminals coupled to the input terminals of the complementary differential amplifier. Two current load p-type field-effect transistors are each coupled in series between one voltage source and a drain terminal of a respective input FET. A current source FET is coupled in series between a common source terminal of the two input n-type field-effect transistors and a low voltage source. Only two FETs are needed to bias all of the current load and source FETs. A complementary folded cascode stage as well as an inverter stage may also be included.

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Pocatello, ID, United States of America

Zhongmin Li