Hong Kong Applied Science and Technology Research Institute Company, Limited

Zhonghui Zhang

Yuxian Zhang

Hing-Mo Lam

Man-Wai Kwan

Kong-Chau Tsang

Man Wai Kwan

Kong Chau Tsang

Xiangyu Liu

Ching-Hong Leung

Syed Mohsin Abbas

Zhuohan Yang

Hin-Tat Chan

Ying-Lun Tsui

Yibing Yao

Described is a method of performing carrier frequency offset (CFO) estimation of physical channels in a mobile communications system. The method comprises the step of performing channel estimation of a received signal on a physical channel based on multiple orthogonal frequency division multiplex (OFDM) symbols in one or more reference signals (RSs). The method includes determining multiple phase rotation values Φ and corresponding time differences s between different OFDM symbols in the one or more RSs over a base phase rotation range comprising +/−π to obtain a first CFO estimation candidate ƒ. The base phase rotation range is extended to provide an extended phase rotation range of greater than +/−π to obtain additional CFO estimation candidates ƒ, ƒ. . . ƒwithin the extended phase rotation range.

Method of large frequency offset estimation for an OFDM communications system using reference signals

Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDDC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

Low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder

Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation. Multiple data shift commands may be utilized such that the plurality of code blocks have an individual shifting command to thereby implement different data shifting with respect to each code block.

Parallel LDPC decoder

The present disclosure relates to methods, devices, and systems for cell identification. For example, the systems, devices, and methods described herein may be used to detecting a secondary synchronization signal (SSS) index. In an aspect of the present disclosure, a method includes detecting, at an electronic device, a first SSS index based on a comparison between a first power value and a first threshold. The first power value is associated with a correlation power result between a received signal from a base station and a local SSS. The method also include determining, at the electronic device, a second threshold based on the first power value, and performing a comparison between a second power value and the second threshold. The second power value is determined based on the received signal.

Cell search in a wireless network

Growing community of inventors

Hong Kong, China

Zhonghui Zhang