Shanghai Huali Integrated Circuit Corporation

Microport Endovascular (shanghai) Co., Ltd.

Shanghai Bluevascular Medtech Co., Ltd.

Shanghai Microport Endovascular Medtech (group) Co., Ltd.

Shanghai Vasolutions Medtech Co., Ltd.

Zhonghua Li

Peng Zhang

Nan Li

Tianpeng Guan

Jianghua Leng

Runling Li

Qing Zhu

Yanbin Gao

Qiyi Luo

Ming Tian

Biao Li

Linlin Zhang

Yongfeng Zhu

Fang Guo

Zhenyu Yuan

Jianchao Han

Dingguo Huang

Wenhui Jiao

Zhong Chen

Shuangxi Ding

Liwen Wang

Yufeng Chen

Zhenghua Miao

Dadong Peng

Shun Xia

Zengzuo Shi

Qingru Ji

Dongmei Yan

FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

FDSOI device structure and preparation method thereof

The present invention provides a filter device, including a filtering part, a constraining part, a stent part, and a connecting part. The filtering part has a first end and a second end opposite to each other. The constraining part is degradable and at least configured to constrain the first end of the filtering part. The stent part has a first end and a second end opposite to each other. The first end of the stent part is connected to the second end of the filtering part, and disposed coaxial with the filtering part. The connecting part is disposed on one or more of the first end of the filtering part and the second end of the stent part, and is configured to connect to an external mechanism, and the constraining part is further configured to constrain the second end of the stent part when the connecting part is disposed at the second end of the stent part. The present invention can be taken out from the human body and can also be partially degraded in the human body so that the occurrence rate of long-term complications is reduced, and secondary surgery can thus be avoided.

Filter device

The present application provides a method for manufacturing FDSOI devices. The method includes steps of: providing a semiconductor structure which comprises a silicon substrate, a buried oxide layer on the silicon substrate, a silicon-on-insulator layer on the buried oxide layer; and a hard mask layer on the silicon-on-insulator layer; performing spin coating of a photoresist on the hard mask layer to form a bulk silicon region; performing plasma anisotropic etching on the bulk silicon region to open a part of the buried oxide layer, and then performing isotropic etching, so that the silicon-on-insulator layer shrinks in the horizontal direction; performing plasma anisotropic etching to etch through the buried oxide layer to form a bulk silicon region trench; performing silicon epitaxial growth in the bulk silicon region trench. The silicon-on-insulator layer is still shrinks after the bulk silicon region trench is formed, as the result, there is no bump on the surface of the silicon-on-insulator layer, thus the process window becomes controllable.

Method for manufacturing FDSOI

An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

An FDSOI device structure and its fabrication method are disclosed. The device includes a silicon substrate; a buried oxide layer on the silicon substrate; a SiGe channel on the buried oxide layer, wherein the SiGe channel has a thickness in a range of 60-100 &#x212b;; a silicon layer on the SiGe channel layer; a metal gate disposed on the silicon layer, and sidewalls attached to both sides of the metal gate; and source-drain regions disposed on the silicon layer at both sides of the metal gate, wherein the source-drain regions are built in raised SiGe layers. The invention discloses a channel forming method for the FDSOI device, the method includes making a SiGe layer and an epitaxially grown silicon layer. This channel has avoided issues such as the low stress of a silicon channel and the Ge diffusion into the gate dielectric as occurred in the conventional process, thereby improving the reliability and performance of the FDSOI device.

The invention discloses a method for manufacturing nickel silicide. The method comprises: Step: providing a semiconductor substrate, wherein the semiconductor substrate has an exposed silicon surface which is a formation region of nickel silicide; Step: carrying out pre-amorphization ion implantation to form an amorphous layer in the formation region of the nickel silicide, wherein an implantation source of the pre-amorphization ion implantation is xenon; and Step: forming the nickel silicide in the formation region of the nickel silicide by self-alignment. Xenon which is a non-radioactive inert gas with the maximum mass is adopted to optimize the uniformity of an interface layer between the amorphous layer and silicon, so that the uniformity of the ohm contact resistance of the nickel silicide is improved.

Method for manufacturing nickel silicide

The invention discloses a P-type MOSFET, a channel region consisting of an N-well is formed in the semiconductor substrate covered with a gate structure; the N-well is formed by overlaying an annealed phosphorus-implanted region, an annealed first arsenic-implanted region and an annealed second arsenic-implanted region, and the first arsenic-implanted region and the second arsenic-implanted region are overlaid to form a threshold voltage regulation region; the implantation depth of the first arsenic-implanted region is greater than that of the second arsenic-implanted region; and an amorphous layer is formed by the first arsenic-implanted region on the semiconductor substrate to improve the implantation uniformity of the second arsenic-implanted region and to decrease the peak surface doping concentration of the second arsenic-implanted region located on the surface of the semiconductor substrate. The invention further discloses a method for manufacturing a P-type MOSFET. The invention can reduce the flicker noises of a device.

P-type MOSFET and method for manufacturing same

A PNA temperature monitoring method comprises: Step 1, forming zero mark layer patterns on a tested silicon substrate; Step 2, forming a nitrogen-doped gate oxide by the following process: growing an oxide layer, doping the oxide layer with nitrogen, and carrying out PNA; Step 3, forming overlay layer patterns, and overlaying the overlay layer patterns and the corresponding zero mark layer patterns to form monitoring structures; and Step 4, measuring overlay values of the overlay layer patterns and the corresponding zero mark layer patterns of the monitoring structures, and regulating a PNA temperature according to the measured overlay values. By adoption of the method, the influence of the PNA temperature on a gate oxide in a two-dimensional plane can be monitored, and then the PNA temperature can be regulated to increase product yield.

PNA temperature monitoring method

A branched stent graft, a convey system comprising thereof and manufacturing method thereof, the branched stent graft includes a main body () and a side branch (), at least a portion of a lowermost stent section of the side branch () closest to the main body () is not stitched to the cover of the side branch from a lower end to an upper end, the at least a portion of the lowermost stent section is located on a side of the side branch corresponding to a folding direction of the side branch. After deployed, the branched stent graft has an effective supporting force at the base portion of the side branch. In addition, during the deployment of the stent, the side branch can expand to a maximal extent even when the positioning is slightly inaccurate. Further, vascular stenosis or occlusion will not be caused even when subsequent endothelialization occurs.

Branched stent graft, delivery system comprising same and method of fabricating same

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Shanghai, China

Zhonghua Li