Via Technologies, Inc.

Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Alliance Semiconductor Co., Ltd.

Zhongding Liu

Shen Li

Jingran Qu

Ken-Ming Li

Joe Bi

Peng Li

Fan Jiang

Zhen-Yu Song

Guofeng Li

Chun-Fu Lin

Gray Pan

Gary Yang

Sally Qu

A temperature sensing system with simplified wiring comprises an in-core temperature sensing component and an out-of-core temperature-evaluation device. The out-of-core temperature-evaluation device provides a plurality of currents to the in-core temperature sensing module in a time-sharing manner. Corresponding to the plurality of currents, the in-core temperature sensing component generates a plurality of potentials to the out-of-core temperature-evaluation device. The out-of-core temperature-evaluation device evaluates a temperature data by performing a difference calculation on the plurality of potentials.

Temperature sensing system

An output stage circuit comprising a bias voltage generator, a first amplifier circuit and a second amplifier circuit is provided. The bias voltage generator is coupled to an output terminal of the output stage circuit to generate a bias voltage according to an output voltage of the output terminal. The first amplifier circuit is coupled to the output terminal, a first power supply terminal and the bias voltage generator, receives a first pre-driving signal, a first predetermined voltage and the bias voltage, and determines whether to transmit a first voltage to serve as the output voltage. The second amplifier circuit is coupled to the output terminal, a second power supply terminal and the bias voltage generator, receives a second pre-driving signal, a second predetermined voltage and the bias voltage, and determines whether to transmit a second voltage to serve as the output voltage.

Output stage circuit

A voltage regulator includes a first control circuit and a first voltage adjusting circuit. The first control circuit receives an output voltage and generates a first control signal according to the output signal. The first voltage adjusting circuit is coupled to the first control circuit, receives the first control signal, and adjusts the output voltage according to the first control signal.

Voltage regulator generating an output voltage according to a coupled load unit

A measurement device measuring a current passing through a detection resistor coupled between a first node and a second node is provided. An interference elimination unit is coupled to the first and second nodes and selectively outputs the voltage of at least one of the first and second nodes according to a control signal. A first voltage-dividing unit is coupled to the interference elimination unit and processes the voltage of the first or second node to generate a first processed signal. A second voltage-dividing unit is coupled to the interference elimination unit and processes the voltage of the first or second node to generate a second processed signal. A processing unit is coupled to the first and second voltage-dividing units to receive the first and second processed signals and calculates the first and second processed signals to obtain the current passing through the detection resistor.

Measuring device

Loop filters are provided, in which a first resistor comprises a first terminal coupled to a first node, and a second terminal coupled to a second node; a first capacitor is coupled between the second node and a ground voltage, a second resistor comprises a first terminal coupled to the first node and a second terminal coupled to a third node. An operational amplifier comprises a non-inversion input terminal coupled to the second node, an inversion input terminal coupled to the third node, and an output terminal, and a second capacitor is coupled between the output terminal of the operational amplifier and the third node.

Loop filters

A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay array clock signal according to the delay control signal. The second delay array receives a power control signal, the first delay array clock signal and the delay control signal. The second delay array is turned on or off according to the power control signal. If the second delay array is turned on, the second delay array delays the first delay array clock signal to output a second delay array clock signal according to the delay control signal. The multiplexer receives a selecting control signal, the first and second delay array clock signals, and outputs the first delay array clock signal or the second delay array clock according to the selecting control signal.

Delay line and delay lock loop

A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.

Delay locked loop with common counter and method thereof

The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of delay cells for respectively delaying the input signal by a certain delay period; and a sub decoding unit for generating a plurality of sub control signals to each of the delay units according to a first control signal and a selecting signal, wherein only delay cell of all the delay units is outputted at a time according to the sub controls signals.

Delay apparatus and method thereof

Comparators outputting offset calibration. A MOS current mode logic (MCML) circuit receives input signals and generates differential logic signals on output terminals thereof, and comprises a calibration unit coupled to the output terminals, calibrating output offsets at the output terminals according to digital calibration codes. An output stage is coupled to the differential logic signals at the output terminals of the MCML circuit to amplify the differential logic signal and generating a comparison resulting signal. By adjusting the digital calibration codes applied to the calibration unit, current on the output terminals can be adjusted, such that output offsets at the output terminals of the MCML circuitcan be eliminated.

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Beijing, China

Zhongding Liu