International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Zhong-Xiang He

Anthony K Stamper

Jeffrey P Gambino

Douglas Duane Coolbaugh

Kai D Feng

Hanyi Ding

Xuefeng Liu

Ebenezer E Eshun

Eric Jeffrey White

Robert Mark Rassel

Anil Kumar Chinthakindi

Qizhi Liu

Fen Chen

Tom C Lee

James Stuart Dunn

Vidhya Ramachandran

Kunal Vaed

Edward Crandal Cooney, Iii

William Joseph Murphy

Natalie Barbara Feilchenfeld

Timothy Dooling Sullivan

Zhenrong Jin

Matthew D Moon

Thomas J Hartswick

Wolfgang Sauter

Alvin Jose Joseph

Daniel C Edelstein

Ping-Chuan Wang

John Michael Cotte

Peter James Lindgren

Ramsey M Hazbun

Felix Patrick Anderson

John J Ellis-Monaghan

Steven H Voldman

Timothy Harrison Daubenspeck

Mark David Jaffe

Christopher David Muzzy

Jeffrey Bowman Johnson

Robert K Leidy

Xiao Hu Liu

Yun Shi

Robert Allen Groves

Thomas L McDevitt

Richard John Rassel

David S Collins

Bradley Alan Orner

Kimball M Watson

Daniel Scott Vanslette

Mete Erturk

David C Thomas

Jonghae Kim

Steven M Shank

Timothy Joseph Dalton

JunJun Li

Wagdi William Abadeer

Michael Joseph Zierak

Randy Lee Wolf

Jeffrey C Maling

Stephen Arthur St Onge

Johnatan A Kantarovsky

Ephrem G Gebreselasie

Jonathan Daniel Chapple-Sokol

BethAnn Rainey

Eric Adler

Jeonghyun Hwang

Ronald Jay Bolam

Richard L Rassel

Jean-Oliver Plouchart

John Chester Malinowski

Mukta G Farooq

James William Adkisson

Xin Ru Wang

Christopher Vincent Jahnes

Chandrasekharan Kothandaraman

Kevin Shawn Petrarca

Herbert Lei Ho

Edmund Juris Sprogis

David Louis Harame

Vincent James McGahay

Roger Allen Booth, Jr

Stephen Ellinwood Luce

Rajendran Krishnasamy

Renata A Camillo-Castillo

Michel J Abou-Khalil

Ning Lu

Theodore James Letavic

Howard Smith Landis

Mark Levy

Kenneth Jay Stein

Richard A Phelps

Deok-Kee Kim

Hongwen Yan

John Matthew Safran

Dan Moy

Yanfeng Wang

Yves T Ngu

Russell T Herrin

Norman Whitelaw Robson

Shawn A Adderly

Gary L Milo

A structure includes a transistor, e.g., HEMT, with a field plate positioned laterally to a side of an active gate and including a first portion extending over the active gate. A dielectric layer isolates a lower surface of the first portion from an upper surface of the active gate. A field plate contact includes interconnect layers located directly over the active gate and electrically coupled to the first portion directly over the active gate. The field plate contact allows electrical operation of the field plate, but also acts as a thermally conductive path from the active gate through the interconnect layers to cool likely hot spots within the transistor.

Field plate structure to reduce self-heating in transistor and related method

A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor layer, a device layer, and heat dissipating structures. The semiconductor layer is over the substrate and the device layer is over the semiconductor layer. The device layer includes a first ohmic contact and a second ohmic contact. The heat dissipating structures are at least through the substrate and the semiconductor layer, and between the first ohmic contact and the second ohmic contact.

High-mobility-electron transistors having heat dissipating structures

The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.

Series inductors

A transistor structure is provided, the structure may be for a high electron mobility transistor (HEMT). The HEMT comprises a channel layer arranged over a substrate, the channel layer may have a top surface. A barrier layer may be arranged over the channel layer. A first opening may be in the barrier layer and extend partially into the channel layer. A first barrier liner may be arranged in the first opening and over the channel layer, the first barrier liner may have a bottom surface. The bottom surface of the first barrier liner may be lower than the top surface of the channel layer.

High electron mobility transistors having barrier liners and integration schemes

Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

Integrated circuit structure with through-metal through-substrate interconnect and method

Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

Transistor with self-aligned gate and self-aligned source/drain terminal(s) and methods

The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

Tight pitch wirings and capacitor(s)

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

Semiconductor structures having low resistance paths throughout a wafer

Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

Integrated circuit including wire structure, related method and design structure

A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

Air gap over transistor gate and related method

The present disclosure relates to semiconductor structures and, more particularly, to segmented guard-ring and chip edge seals and methods of manufacture. The structure includes: a guard ring structure formed in a low-k dielectric material; and an edge seal structure formed through the low-k dielectric material to at least a substrate underneath the low-k dielectric material.

Segmented guard-ring and chip edge seals

Growing community of inventors

Essex Junction, VT, United States of America

Zhong-Xiang He